Please enter a valid full or partial manufacturer part number with a minimum of 3 letters or numbers

    VIAL Search Results

    SF Impression Pixel

    VIAL Price and Stock

    Kyocera AVX Components MD035R105KMA-VIAL

    - Bulk (Alt: MD035R105KMA-VIAL)
    Distributors Part Package Stock Lead Time Min Order Qty Price Buy
    Avnet Americas MD035R105KMA-VIAL Bulk 20 Weeks 200
    • 1 -
    • 10 -
    • 100 -
    • 1000 -
    • 10000 -
    		Get Quote

    Kyocera AVX Components M39014/22-0247-VIAL

    MR EST. REL. - Bulk (Alt: M39014/22-0247-VIA)
    Distributors Part Package Stock Lead Time Min Order Qty Price Buy
    Avnet Americas M39014/22-0247-VIAL Bulk 200
    • 1 -
    • 10 -
    • 100 -
    • 1000 $23.42677
    • 10000 $23.42677
    		Buy Now

    Kyocera AVX Components MD035R334KMA-VIAL

    DIP STD ALPHA - Bulk (Alt: MD035R334KMA-VIAL)
    Distributors Part Package Stock Lead Time Min Order Qty Price Buy
    Avnet Americas MD035R334KMA-VIAL Bulk 200
    • 1 -
    • 10 -
    • 100 -
    • 1000 $27.11484
    • 10000 $27.11484
    		Buy Now

    Shure MVI/A-LTG

    Mvi Digital Audio Interface + Usb & Lightning Cable |SHURE MVI/A-LTG
    Distributors Part Package Stock Lead Time Min Order Qty Price Buy
    Newark MVI/A-LTG Bulk 1
    • 1 -
    • 10 -
    • 100 -
    • 1000 -
    • 10000 -
    		Buy Now

    DigitHead Inc 7/8X3.5VIAL NP

    Vial Only 7/8" Dia X 3-1/2" (1700 Per Case) |Digithead 7/8X3.5VIAL NP
    Distributors Part Package Stock Lead Time Min Order Qty Price Buy
    Newark 7/8X3.5VIAL NP Bulk 1,700
    • 1 -
    • 10 -
    • 100 -
    • 1000 -
    • 10000 -
    		Buy Now
    Find more VIAL price and stock on Findchips.com

    VIAL Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    Untitled

    Abstract: No abstract text available
    Text: Standard Products UT4090 RadHard FPGA Advanced Data Sheet February 21, 2001 FEATURES q 0.35µm four-layer metal non-volatile CMOS process for smallest die sizes q One-time programmable, ViaLink TM antifuse technology for personalization q 150 MHz 16-bit counters, 200 MHz datapaths, 80+ MHz


    Original     		PDF UT4090 16-bit MIL-STD-883 MIL-PRF-38535. MIL-STD-1835. 208-pin

    16X24B

    Abstract: CF160 PF100 PF144 PL84 CPGA Package Diagram
    Text: QL16x24B pASIC 1 Family Very-High-Speed CMOS FPGA Rev C pASIC HIGHLIGHTS …4,000 usable ASIC gates, 122 I/O pins Very High Speed – ViaLink metal-to-metal programmable–via antifuse technology, allows counter speeds over 150 MHz and logic cell delays of under 2 ns.


    Original     		PDF QL16x24B 16-by-24 84-pin 100-pin 144-pin 160-pin 16-bit 16x24B CF160 PF100 PF144 PL84 CPGA Package Diagram

    PL84

    Abstract: ql16x24bl PF100 PF144
    Text: QL16x24BL pASIC 1 Family Low Power 3.3 Volt Operation FPGA pASIC HIGHLIGHTS High Speed – ViaLink metal-to-metal programmable–via antifuse technology, allows counter speeds over 80 MHz at 3.3 Volt operation. 5V Tolerant I/Os – Support interface to 5 Volt CMOS, NMOS and


    Original     		PDF QL16x24BL 16-by-24 84-pin 100-pin 144-pin QL16x24B QL16x24 16x24BL PF144 84-pin PL84 ql16x24bl PF100

    QL4090

    Abstract: pASIC 1 Family 160CQFP 208-CQFP
    Text: QL16x24B pASIC 1 Family Very-High-Speed CMOS FPGA Rev C pASIC HIGHLIGHTS …4,000 usable ASIC gates, 122 I/O pins Very High Speed – ViaLink metal-to-metal programmable–via antifuse technology, allows counter speeds over 150 MHz and logic cell delays of under 2 ns.


    Original     		PDF QL16x24B 16-by-24 84-pin 100-pin 144-pin 160-pin 16-bit V144-TQFP QL24x32B QL4090 pASIC 1 Family 160CQFP 208-CQFP

    PF144

    Abstract: PQ208 QL24X32B-1PQ208C
    Text: QL24x32B pASIC 1 Family Very-High-Speed CMOS FPGA pASIC HIGHLIGHTS …8,000 usable ASIC gates, 180 I/O pins Very High Speed – ViaLink metal-to-metal programmable–via antifuse technology, allows counter speeds over 150 MHz and logic cell delays of under 2 ns.


    Original     		PDF QL24x32B 24-by-32 144-pin 208-pin 24x32B PQ208 M/883C PF144 PF144 QL24X32B-1PQ208C

    QL8X12B

    Abstract: PF100 pASIC 1 Family circuit diagram of Tri-State Buffer using CMOS
    Text: QL8X12B pASIC 1 Family Very-High-Speed CMOS FPGA Rev B pASIC HIGHLIGHTS Very High Speed – ViaLink metal-to-metal programmable–via antifuse technology, allows counter speeds over 150 MHz and logic cell delays of under 2 ns. …1,000 usable ASIC gates,


    Original     		PDF QL8X12B 8-by-12 44-pin 68-pin 100-pin 16-bit QL8X12B PF100 pASIC 1 Family circuit diagram of Tri-State Buffer using CMOS

    PQFP208

    Abstract: CCGA 484 socket CLGA484 PBGA280 PBGA484 5962-0422 SDRAM edac transistor smd qe UT6325 RAM EDAC SEU
    Text: Aeroflex Colorado Springs RadHard Eclipse FPGA Frequently Asked Questions NOTE - FAQs WILL BE UPDATED ON A REGULAR BASIS Introduction: QuickLogic has licensed their metal-to-metal VialinkTM technology to Aeroflex Colorado Springs (Aeroflex). The agreement calls for Aeroflex to have access to QuickLogic’s


    Original     		PDF UT6325. PQFP208 CCGA 484 socket CLGA484 PBGA280 PBGA484 5962-0422 SDRAM edac transistor smd qe UT6325 RAM EDAC SEU

    piher spain potentiometer

    Abstract: piher spain Piher International
    Text: v01 Navarra de Componentes Electrónicos, S.A. NACESA Factory & Headquarters Polígono Industrial Municipal Vial T2, Nº 22 31500 Tudela Spain Tel: +34-948-820450 Fax: +34-948-824050 Email: sales@piher.net PIHER INTERNATIONAL LTD Unit 20 Ash Kembrey Park Swindon


    Original     		PDF 11F-1, piher spain potentiometer piher spain Piher International

    tms320cXX

    Abstract: TMS57002 tms320c26 dsk TMS320C26 TMS320C31 TMS DASP 93C26 h004 ti31 CS4248
    Text: S.E.E.D. Mr. M. Marani Viale Roma 88/A 54100 Massa MS Italy (+39) 585 792990 Fax: (+39) 585 792989 e-mail: mc4453@mclink.it Company Background S.E.E.D. is an association of electronic engineers and computer science specialists, founded in 1993 and based in Massa, Italy. S.E.E.D. operates in the DSP field giving consulting about specific applications of the customers and is able to design or integrate


    Original     		PDF mc4453 RS-232 RS232 TMS57002 CS4225 TMS320C26 tms320cXX TMS57002 tms320c26 dsk TMS320C26 TMS320C31 TMS DASP 93C26 h004 ti31 CS4248

    seed

    Abstract: No abstract text available
    Text: S.E.E.D. Mr. M. Marani Viale Roma 88/A 54100 Massa Italy +39 335 372256 e-mail: mc4453@mclink.it Company Background S.E.E.D. is an association of Electronic Engineers and Computer Science Specialists, born in 1993 and based in Massa, Italy. S.E.E.D. operates in DSP field giving consulting


    Original     		PDF mc4453 TMS320C1x, TMS320C2x, TMS320C3x, TMS320C4x, TMS320C5x seed

    1000L

    Abstract: PF100 QL8X12Bl
    Text: QL8x12BL Wild Cat 1000L Low Power 3.3 Volt Operation, 1K Gate FPGA 2 High Speed – ViaLinkTM metal-to-metal programmable–via antifuse technology, allows counter speeds over 80 MHz at 3.3 Volt operation. 5V Tolerant I/Os – Support interface to 5 Volt CMOS, NMOS and


    Original     		PDF QL8x12BL 1000L 8-by-12 with1000 44-pin 68-pin 100-pin QL8x12B 8X12BL 1000L PF100 QL8X12Bl

    QL24X32B-1PQ208C

    Abstract: PF144 PQ208
    Text: QL24x32B Wild Cat 8000 Very-High-Speed 8K 24K Gate CMOS FPGA 2 .8000 usable gates, 180 I/O pins Very High Speed – ViaLinkTM metal-to-metal programmable–via antifuse technology, allows counter speeds over 150 MHz and logic cell delays of under 2 ns.


    Original     		PDF QL24x32B 24-by-32 144pin 208-pin Viewlog-55, 24x32B PQ208 M/883C MIL-STD-883D PF144 QL24X32B-1PQ208C PF144

    pASIC 1 Family

    Abstract: pASIC 3 Family pASIC1 GAL Gate Array Logic CMOS 4000 Logic Family
    Text: pASIC 1 FAMILY ViaLink Technology Very-High-Speed CMOS FPGAs 2 Very High Speed – ViaLink metal-to-metal, programmable-via antifuse technology ensures useful internal logic function speeds at over 100 MHz, and logic cell delays of under 2 ns. High Usable Density – Up to 8,000 “gate array” gates, equivalent to


    Original     		PDF 14-input pASIC 1 Family pASIC 3 Family pASIC1 GAL Gate Array Logic CMOS 4000 Logic Family

    QuickLogic ql16x24b-1pl84c

    Abstract: QL16X24B PF144 cmos io QL16X24BH TQFP 144 PACKAGE CF160 PF100 PL84
    Text: QL16x24B/QL16x24BH Wild Cat 4000 Very-High-Speed 4K 12K Gate CMOS FPGA Rev B .4000 usable gates, 122 I/O pins Very High Speed – ViaLinkTM metal-to-metal programmable–via antifuse technology, allows counter speeds over 150 MHz and logic cell delays of under 2 ns.


    Original     		PDF QL16x24B/QL16x24BH 16-by-24 84pin 100-pin 144-pin 160pin 16-bit QL16x24BH QuickLogic ql16x24b-1pl84c QL16X24B PF144 cmos io TQFP 144 PACKAGE CF160 PF100 PL84

    report on PLCC

    Abstract: 40673 plcc 68 QL8X12A reliability report solar cell Amorphous 40673 equivalent ql8x12 144TQFP PACKAGE QL8X12B
    Text: SUMMARY August 1997 The pASIC device is a highly reliable Field Programmable Gate Array. The addition of the ViaLink to a CMOS process does not measurably increase the failure rate of the pASIC devices above that of normal CMOS logic products. The following is the summary of the High


    Original     		PDF

    ttl logic gates

    Abstract: pASIC 1 Family ttl and gate
    Text: pASIC 1 Family ViaLink Technology Very-High-Speed CMOS FPGAs FAMILY HIGHLIGHTS Very High Speed – ViaLink metal-to-metal, programmable-via antifuse technology ensures useful internal logic function speeds at over 100 MHz, and logic cell delays of under 2 ns.


    Original     		PDF 14-input MIL-STD-883D, ttl logic gates pASIC 1 Family ttl and gate

    transistor 1f sot-23

    Abstract: sot23 AJ motorola sot 23 marking transistor marking code SOT-23 BC817B marking 1F transistor sot-23 transistor marking code SOT-23 2F marking 1P sot-23 sot 23 transistor 2f sot transistor pinout
    Text: oatrif ©® SOT 23 Microminiature Space Saving Alternatives for Discrete Devices • Packaging — M otorola standard shipping A wide variety of discrete components from method for SOT’s is in vials; additionally, in M otorola's repertoire of reliability-proven sem icon­


    OCR Scan     		PDF BCX70J BC81740 BC850B BC817B BCW72 BCX704 BC817-25 BCX70G BC847A BC817-16 transistor 1f sot-23 sot23 AJ motorola sot 23 marking transistor marking code SOT-23 marking 1F transistor sot-23 transistor marking code SOT-23 2F marking 1P sot-23 sot 23 transistor 2f sot transistor pinout

    Untitled

    Abstract: No abstract text available
    Text: Q L 8X 12B pASIC 1 Family Very-High-Speed CMOS FPGA Rev B pASIC HIGHLIGHTS Very High Speed - ViaLink" metal-to-metal programmable-via antifuse technology, allows counter speeds over 150 MHz and logic cell delays of under 2 ns. . 1,000 usable ASIC gates,


    OCR Scan     		PDF 8-by-12 44-pin 68-pin 100-pin 16-bit

    Untitled

    Abstract: No abstract text available
    Text: QL24x32BL pASIC 1 Family Low Power 3.3 Volt Operation FPGA pASIC HIGHLIGHTS High Speed - ViaLink" metal-to-metal programmable-via antifuse technology, allows counter speeds over 80 MHz at 3.3 Volt operation. 5Y Tolerant I/Os - Support interface to 5 Volt CMOS, NMOS and


    OCR Scan     		PDF QL24x32BL 24-by-32 144-pin 208-pin QL24x32B 24x32BL PQ208 PF144 144-pin

    Untitled

    Abstract: No abstract text available
    Text: QL8x12 pASIC 1 FAMILY Very-High-Speed IK 3K Gate CMOS FPGA pASIC HIGHLIGHTS Very High Speed - ViaLink metal-to-metal programmable-via antifuse technology, allows counter speeds over 100 MHz, and logic cell delays of under 4 ns. High Usable Density - An 8-by-12 array of 96 logic cells provides


    OCR Scan     		PDF QL8x12 8-by-12 68-pin 100-pin 16-bit

    L16X2

    Abstract: ic logic gates
    Text: pASIC 1 FAMILY ViaLink Technology Very-High-Speed CMOS FPGAs gj V ery H igh S p eed - V iaL ink m etal-to-m etal, program m able-via an ti­ fuse technology ensures useful internal logic function speeds at over 100 M H z, and logic cell delays o f under 2 ns.


    OCR Scan     		PDF 14-input L16X2 ic logic gates

    DO-213AB MELF

    Abstract: 12MMTAPE
    Text: PACKAGING DATA Surface Mount Products BULK PACK QUANTITY PER CONTAINER PACKAGE PLASTIC BAGS VIALS DO-213AA MELF, LL34,SOD-80 5,000 500 DO-213AB (MELF, LL41) 5,000 500 TAPE & REEL PACKAGE TAPE WIDTH (MM) REEL SIZE (INCHES) 7 2,000 8 13 10,000 7 1,500 12 13


    OCR Scan     		PDF DO-213AA OD-80) DO-213AB DC-213AA DO-213AB MELF 12MMTAPE

    sod80

    Abstract: No abstract text available
    Text: CLD Packing options Leaded Devices BULK PACKED, ANTISTATIC BOX TAPED AND REELED, STANDARD AXIAL 2,500/BOX 2,500/REEL ADD BK SUFFIX ADD TR SUFFIX 1,000/VIAL 2,500/REEL 10,000/REEL ADD BK SUFFIX ADD TR SUFFIX ADD TR 13 SUFFIX Surface Mount Devices BULK PACKED, ANTISTATIC VIAL


    OCR Scan     		PDF 500/BOX 500/REEL 000/VIAL 000/REEL OD-80 sod80

    QL12x16B

    Abstract: ic 236
    Text: Q L12x16B WildCat 2000 Very-High-Speed 2K 6K Gate CMOS FPGA pASIC HIGHLIGHTS .6000 total available gates, 88 input pins Q Very High Speed - ViaLink metal-to-metal programmable-via anti-fuse technology, allows counter speeds over 150 MHz and logic cell delays of


    OCR Scan     		PDF L12x16B 12-by-16array 68and 84-pin 100-pin QL12xl6 16-bit QL12x16B 12xl6B ic 236