Contextual Info: DS90CR486 www.ti.com SNLS149C – FEBRUARY 2003 – REVISED MARCH 2013 DS90CR486 133MHz 48-Bit Channel Link Deserializer 6.384 Gbps Check for Samples: DS90CR486 FEATURES 1 • • • • • • 2 • • • • • Up to 6.384 Gbps Throughput 66MHz to 133MHz Input Clock Support

AN-1059

Abstract: AN-1163 DS90C387 DS90CF384A DS90CF386 DS90CF388
Contextual Info: DS90C387/DS90CF388 Dual Pixel LVDS Display Interface LDI -SVGA/QXGA General Description Features The DS90C387/DS90CF388 transmitter/receiver pair is designed to support dual pixel data transmission between Host and Flat Panel Display up to QXGA resolutions. The transmitter converts 48 bits (Dual Pixel 24-bit color) of CMOS/TTL

Contextual Info: DS90CR483A, DS90CR484A www.ti.com SNLS291A – APRIL 2008 – REVISED APRIL 2013 DS90CR483A / DS90CR484A 48-Bit LVDS Channel Link SER/DES – 33 - 112 MHz Check for Samples: DS90CR483A, DS90CR484A FEATURES 1 • • • 2 • • • • • • • • •

Contextual Info: DS90CR481, DS90CR482 www.ti.com SNLS137D – NOVEMBER 2000 – REVISED APRIL 2013 DS90CR481 / DS90CR482 48-Bit LVDS Channel Link SER/DES − 65 - 112 MHz Check for Samples: DS90CR481, DS90CR482 FEATURES 1 • • • • 2 • • • • • • • • 3.168 Gbits/sec Bandwidth with 66 MHz Clock

DS90C387R

Contextual Info: November 2000 DS90C387R 85MHz Dual 12-Bit Double Pumped Input LDI Transmitter - VGA/UXGA General Description The DS90C387R transmitter is designed to support pixel data transmission from a Host to a Flat Panel Display up to UXGA resolution. It is designed to be compatible with Graphics Memory Controller Hub GMCH by implementing two

Contextual Info: September 1999 DS90C387/DS90CF388 Dual Pixel LVDS Display Interface LDI -SVGA/QXGA General Description The DS90C387/DS90CF388 transmitter/receiver pair is designed to support dual pixel data transmission between Host and Flat Panel Display up to QXGA resolutions. The transmitter converts 48 bits (Dual Pixel 24-bit color) of CMOS/TTL

Contextual Info: DS90CR483 / DS90CR484 48-Bit LVDS Channel Link Serializer/Deserializer General Description The DS90CR483 transmitter converts 48 bits of CMOS/TTL data into eight LVDS Low Voltage Differential Signaling data streams. A phase-locked transmit clock is transmitted in

dual pixel lvds

Abstract: CMOS QXGA
Contextual Info: DS90C387A,DS90CF388A DS90C387A/DS90CF388A Dual Pixel LVDS Display Interface / FPD-Link Literature Number: SNLS065D DS90C387A/DS90CF388A Dual Pixel LVDS Display Interface / FPD-Link General Description The DS90C387A/DS90CF388A transmitter/receiver pair is designed to support dual pixel data transmission between

buffer 24V

Abstract: scanner block diagram flatbed scanner controller canon line scan sensor application notes 300DPI cmos image sensor canon bipolar stepper motor circuits high current canon CIS 300dpi
Contextual Info: LM9830 LM9830 36-Bit Color Document Scanner Literature Number: SNOS444B N LM9830 36-Bit Color Document Scanner General Description scan resolution and pixel depth for maximum scan speed. • Stepper motor control tightly coupled with buffer management to maximize data transfer efficiency.

f4ha

Abstract: MX08 LM4560 ymf262 opl3 SNAS029
Contextual Info: LM4560 LM4560 Advanced PCI Audio Accelerator Literature Number: SNAS029 LM4560 Advanced PCI Audio Accelerator General Description LM4560 is an advanced PCI audio accelerator providing full legacy compatibility, wavetable synthesis, DirectMusic, DirectSound, and DirectSound3D on a single chip for the highperformance, cost-sensitive consumer market. It supports

DS90CR482

Abstract: DS90CR483 DS90CR484 DS90CR485 DS90CR486 PRBS-15 termination sense
Contextual Info: DS90CR485 133MHz 48-bit Channel Link Serializer 6.384 Gbps General Description The DS90CR485 serializes the 24 LVCMOS/LVTTL double edge inputs (48 bits data latched in per clock cycle) onto 8 Low Voltage Differential Signaling (LVDS) streams. A phaselocked transmit clock is also in parallel with the data streams

Contextual Info: DS90CR483A, DS90CR484A www.ti.com SNLS291A – APRIL 2008 – REVISED APRIL 2013 DS90CR483A / DS90CR484A 48-Bit LVDS Channel Link SER/DES – 33 - 112 MHz Check for Samples: DS90CR483A, DS90CR484A FEATURES 1 • • • 2 • • • • • • • • •

lvds 40 pin pinout

Abstract: 100L DS90CR483 DS90CR483VJD DS90CR484 DS90CR484VJD VJD100A
Contextual Info: DS90CR483 / DS90CR484 48-Bit LVDS Channel Link SER/DES — 33 - 112 MHz General Description The DS90CR483 transmitter converts 48 bits of CMOS/TTL data into eight LVDS Low Voltage Differential Signaling data streams. A phase-locked transmit clock is transmitted in

Contextual Info: DS90CR481, DS90CR482 www.ti.com SNLS137C – MAY 2004 – REVISED JANUARY 2006 48-Bit LVDS Channel Link SER/DES − 65 - 112 MHz Check for Samples: DS90CR481, DS90CR482 FEATURES 1 • • • • 2 • • 3.168 Gbits/sec bandwidth with 66 MHz Clock 5.376 Gbits/sec bandwidth with 112 MHz Clock

FLM G12

Abstract: AN-1059 DS90C387 DS90CF388 "DUAL pixel" Programmable LVDS Receiver 24-Bit RGB
Contextual Info: July 2000 DS90C387/DS90CF388 Dual Pixel LVDS Display Interface LDI -SVGA/QXGA General Description The DS90C387/DS90CF388 transmitter/receiver pair is designed to support dual pixel data transmission between Host and Flat Panel Display up to QXGA resolutions. The transmitter converts 48 bits (Dual Pixel 24-bit color) of CMOS/TTL

Contextual Info: FPD85308 FPD85308 Panel Timing Controller Literature Number: SNOS531 May 2001 FPD85308 Panel Timing Controller General Description Features The FPD85308 Panel Timing Controller is an integrated FPD-Link based TFT-LCD timing controller. It resides on the flat panel display and provides the interface signal routing

LM4560

Contextual Info: Semiconductor LM4560 Advanced PCI Audio Accelerator General Description The LM4560 integrates a 64-voice wave table engine with per voice effect processing capability. It supports the upcom­ ing Microsoft DirectMusic API and is fully compatible with DLS Level 1 downloadable samples specification. The

FLM G12

Abstract: EL B17
Contextual Info: Semiconductor PRELIMINARY April 1999 DS90C387/DS90CF388 Dual Pixel LVDS Display Interface LDQ-SVGA/QXGA General Description The DS90C387/DS90CF388 transmitter/receiver pair is de­ signed to support dual pixel data transmission between Host and Flat Panel Display up to QXGA resolutions. The trans­

SmD TRANSISTOR a42

Abstract: TRANSISTOR BC 136 TRANSISTOR BC 157 transistor BC 945 TRANSISTOR BC 187 SNA10A TRANSISTOR BC 413 MO-220-WGGD-2 pdf on BC 187 TRANSISTOR MO-220-WKKD-2
Contextual Info: Plastic Package Dimensional/Thermal Data The following table identifies all of the plastic package configurations and pin counts per package type offered by National Semiconductor. In addition, the table provides dimensional and thermal data for each of the plastic packages

Contextual Info: DS90CR485 www.ti.com SNLS143D – FEBRUARY 2003 – REVISED MARCH 2013 DS90CR485 133MHz 48-bit Channel Link Serializer 6.384 Gbps Check for Samples: DS90CR485 FEATURES DESCRIPTION • • • • • • • • • • • The DS90CR485 serializes the 24 LVCMOS/LVTTL

HSYNC, VSYNC, DE

Abstract: AN-1059 DS90C387 DS90C387A DS90CF384A DS90CF388 DS90CF388A 101-32016 101-32013 CMOS QXGA
Contextual Info: DS90C387A/DS90CF388A Dual Pixel LVDS Display Interface / FPD-Link General Description The DS90C387A/DS90CF388A transmitter/receiver pair is designed to support dual pixel data transmission between Host and Flat Panel Display up to QXGA resolutions. The transmitter converts 48 bits Dual Pixel 24-bit color of

SCANSTA112

Abstract: A001 SCANPSC110 SCANSTA111 STA112 PSC110
Contextual Info: SCANSTA112 7-port Multidrop IEEE 1149.1 JTAG Multiplexer General Description The SCANSTA112 extends the IEEE Std. 1149.1 test bus into a multidrop test bus environment. The advantage of a multidrop approach over a single serial scan chain is improved test throughput and the ability to remove a board

DS90CR483VJD

Contextual Info: DS90CR483,DS90CR484 DS90CR483 / DS90CR484 48-Bit LVDS Channel Link SER/DES — 33 - 112 MHz Literature Number: SNLS047G DS90CR483 / DS90CR484 48-Bit LVDS Channel Link SER/DES — 33 - 112 MHz General Description The DS90CR483 transmitter converts 48 bits of CMOS/TTL

LVDS 8BIT Tx. 2002 DIGITAL VIEW LTD

Contextual Info: DS90CR483 / DS90CR484 48-Bit LVDS Channel Link Serializer/Deserializer General Description The DS90CR483 transmitter converts 48 bits of CMOS/TTL data into eight LVDS Low Voltage Differential Signaling data streams. A phase-locked transmit clock is transmitted in