XC9572F Search Results

XC9572F Datasheets (1)

Part	ECAD Model	Manufacturer	Description	Curated	Datasheet Type	PDF
XC9572 Family		Xilinx	XC9572: 5V ISP CPLD Family		Original	PDF

XC9572F Datasheets Context Search

Catalog Datasheet	MFG & Type	PDF	Document Tags
X5880 Abstract: XC9500 XC95108 XC95144 XC95180 XC95216 XC95288 XC9536 XC9572 xc9536 44 pin vqfp Text:  XC9500 In-System Programmable CPLD Family January, 1997 Version 1.1 Preliminary Product Information Features instruction set allows version control of programming patterns and in-system debugging. In-system programming throughout the full device operating range and a minimum	Original	PDF	XC9500 X5880 XC95108 XC95144 XC95180 XC95216 XC95288 XC9536 XC9572 xc9536 44 pin vqfp
TTL32 Abstract: TTL20 S124 TTL-20 TTL16 HW-133 diode b27 TTL41 TTL-30 TTL38 Text: ZONE P1 TTL0 D3 TTL3 A2 TTL6 A3 D2 D1 D0 S1-17 S1-20 S1-19 S1-18 TTL1 3/27/95 EWR FE 02 CHANGE PER DCN 7106 7/18/95 JWS ZZ 03 CHANGE PER DCN #7451 9/26/95 EWR ZZ P1 D4 B1 S1-22 S1-25 D6 TTL2 TTL4 B2 TTL5 C2 TTL7 B3 TTL8 C3 TTL10 B4 TTL11 C4 A5 TTL12 B5 TTL13	Original	PDF	S1-17 S1-20 S1-19 S1-18 S1-22 S1-25 TTL11 S1-24 S1-26 TTL10 TTL32 TTL20 S124 TTL-20 TTL16 HW-133 diode b27 TTL41 TTL-30 TTL38
PC84 84-Pin Plastic Leaded Chip Carrier Abstract: XC9572 PC84 PC84 XC9500 XC9572 PC84 84-Pin Plastic Leaded Chip Carrier PLCC Text:  XC9572 In-System Programmable CPLD March, 1997 Version 1.1 Product Specification Features Description • 7.5 ns pin-to-pin logic delays on all pins • fCNT to 125 MHz • 72 macrocells with 1,600 usable gates • Up to 72 user I/O pins • 5 V in-system programmable (ISP)	Original	PDF	XC9572 36V18 84-Pin PQ100 100-Pin TQ100 XC9572 XC9572F PQ100 PC84 84-Pin Plastic Leaded Chip Carrier XC9572 PC84 PC84 XC9500 PC84 84-Pin Plastic Leaded Chip Carrier PLCC
xc9572 Abstract: PC84 84-Pin Plastic Leaded Chip Carrier Text: flXILINX XC9572 In-System Programmable CPLD January, 1997 Version 1.0 Prelim inary Product Specification Features Description • • 7.5 ns pin-to-pin logic delays on all pins fCN-\|-to 125 MHz • • • 72 m acrocells with 1,600 usable gates Up to 72 user I/O pins	OCR Scan	PDF	XC9572 36V18 84-Pin PQ100 100-Pin TQ100 TQ100 XC9572 PC84 84-Pin Plastic Leaded Chip Carrier
XC9572X Abstract: xc9536 44 pin vqfp XC9572F 33vy XC9500F Text: KXILINX XC9500 In-System Programmable CPLD Family Jan ua ry, 1997 V ersion 1.1 Preliminary Product Information Features instruction set allows version control of programming pat terns and in-system debugging. In-system programming throughout the full device operating range and a minimum	OCR Scan	PDF	XC9500 XC9572X xc9536 44 pin vqfp XC9572F 33vy XC9500F