1.8 MM PITCH BGA Search Results

1.8 MM PITCH BGA Result Highlights (5)

Part	Manufacturer	Description
D6417750RBP240DV	Renesas Electronics Corporation	32-bit Microcontrollers, BGA, /
HD6417750RBP240	Renesas Electronics Corporation	32-bit Microcontrollers, BGA, /
HD6417750RBP200V	Renesas Electronics Corporation	32-bit Microcontrollers, BGA, /
7MMV4101S10BGI	Renesas Electronics Corporation	128K X 24 MCM BGA 3.3
7MMV4101S15BG	Renesas Electronics Corporation	128K X 24 MCM BGA 3.3

1.8 MM PITCH BGA Datasheets Context Search

Catalog Datasheet	MFG & Type	Document Tags	PDF
gs8182d18d200 Abstract: No abstract text available Text: GS8182D18D-200/167 200 MHz–167 MHz 1.8 V VDD 1.8 V and 1.5 V I/O 18Mb Burst of 4 SigmaQuad-II SRAM 165-Bump BGA Commercial Temp Industrial Temp SigmaRAM Family Overview Bottom View 165-Bump, 13 mm x 15 mm BGA 1 mm Bump Pitch, 11 x 15 Bump Array JEDEC Std. MO-216, Variation CAB-1	Original	GS8182D18D-200/167 165-Bump 165-bump, 144Mb 8182Dxx gs8182d18d200	PDF
Untitled Abstract: No abstract text available Text: GS8182Q18/36D-200/167/133 200MHz–133MHz 1.8 V VDD 1.8 V and 1.5 V I/O 18Mb Burst of 2 SigmaQuad-II SRAM 165-Bump BGA Commercial Temp Industrial Temp SigmaRAM Family Overview Bottom View 165-Bump, 13 mm x 15 mm BGA 1 mm Bump Pitch, 11 x 15 Bump Array JEDEC Std. MO-216, Variation CAB-1	Original	GS8182Q18/36D-200/167/133 165-Bump 165-bump, 144Mb 200MHz 133MHz 8182Qxx	PDF
CYUSB301X Abstract: No abstract text available Text: CYUSB301X EZ-USB FX3 SuperSpeed USB Controller Features • Independent power domains for core and I/O ❐ Core operation at 1.2 V 2 ❐ I S, UART, and SPI operation at 1.8 to 3.3 V 2 ❐ I C operation at 1.2 V ■ 10- x 10-mm, 0.8-mm pitch Pb-free ball grid array BGA	Original	CYUSB301X 10-mm CYUSB301X	PDF
Untitled Abstract: No abstract text available Text: Preliminary GS8342D08/09/18/36E-400/300/250/200/167 36Mb SigmaQuad-II Burst of 4 SRAM 165-Bump BGA Commercial Temp Industrial Temp 167 MHz–400 MHz 1.8 V VDD 1.8 V and 1.5 V I/O Features • Simultaneous Read and Write SigmaQuad Interface • JEDEC-standard pinout and package	Original	GS8342D08/09/18/36E-400/300/250/200/167 165-Bump 165-bump, 144Mb 165-Pin	PDF
GS818 Abstract: No abstract text available Text: Preliminary GS8662S08/09/18/36E-333/300/250/200/167 167 MHz–333 MHz 1.8 V VDD 1.8 V and 1.5 V I/O 72Mb Burst of 2 DDR SigmaSIO-II SRAM 165-Bump BGA Commercial Temp Industrial Temp Features • Simultaneous Read and Write SigmaSIO Interface • JEDEC-standard pinout and package	Original	GS8662S08/09/18/36E-333/300/250/200/167 165-Bump 165-bump, 144Mb 165-Pin GS866x36E-300T. GS818	PDF
Untitled Abstract: No abstract text available Text: Preliminary GS8342Q08/09/18/36E-300/250/200/167 36Mb SigmaQuad-II Burst of 2 SRAM 165-Bump BGA Commercial Temp Industrial Temp 167 MHz–300 MHz 1.8 V VDD 1.8 V and 1.5 V I/O Features • Simultaneous Read and Write SigmaQuad Interface • JEDEC-standard pinout and package	Original	GS8342Q08/09/18/36E-300/250/200/167 165-Bump 165-bump, 144Mb GS8342Q08E-200I GS8342Q08\E-167I 165-Pin GS8342x36E-200T.	PDF
k2333 Abstract: GS8342T GS8342T36 Text: Preliminary GS8342T08/18/36E-400/300/250/200/167 36Mb SigmaCIO DDR-II Burst of 2 SRAM 165-Bump BGA Commercial Temp Industrial Temp 167 MHz–400 MHz 1.8 V VDD 1.8 V and 1.5 V I/O Features • Simultaneous Read and Write SigmaCIO Interface • Common I/O bus	Original	GS8342T08/18/36E-400/300/250/200/167 165-Bump 165-bump, 144Mb GS834x36E-300T. GS8342T k2333 GS8342T GS8342T36	PDF
Untitled Abstract: No abstract text available Text: Preliminary GS8662D08/09/18/36E-333/300/250/200/167 72Mb SigmaQuad-II Burst of 4 SRAM 165-Bump BGA Commercial Temp Industrial Temp 167 MHz–333 MHz 1.8 V VDD 1.8 V and 1.5 V I/O Features • Simultaneous Read and Write SigmaQuad Interface • JEDEC-standard pinout and package	Original	GS8662D08/09/18/36E-333/300/250/200/167 165-Bump 165-bump, 144Mb 165-Pin	PDF
Untitled Abstract: No abstract text available Text: Preliminary GS8662R08/09/18/36E-333/300/250/200/167 72Mb SigmaCIO DDR-II Burst of 4 SRAM 165-Bump BGA Commercial Temp Industrial Temp 167 MHz–333 MHz 1.8 V VDD 1.8 V and 1.5 V I/O Features • Simultaneous Read and Write SigmaCIO Interface • Common I/O bus	Original	GS8662R08/09/18/36E-333/300/250/200/167 165-Bump 165-bump, 144Mb GS866x36E-300T. GS8662Rxx	PDF
ECHO schematic diagrams Abstract: No abstract text available Text: Preliminary GS8170LW18/36/72C-333/300/250 18Mb Σ1x1 Late Write SigmaRAM SRAM 209-Bump BGA Commercial Temp Industrial Temp 250 MHz–333 MHz 1.8 V VDD 1.8 V and 1.5 V I/O Features • Late Write mode • Pipeline read operation • JEDEC-standard SigmaRAM™ pinout and package	Original	GS8170LW18/36/72C-333/300/250 209-Bump 209-bump, 8170LW18 ECHO schematic diagrams	PDF
Untitled Abstract: No abstract text available Text: Preliminary GS8342Q08/09/18/36E-300/250/200/167 36Mb SigmaQuad-II Burst of 2 SRAM 165-Bump BGA Commercial Temp Industrial Temp 167 MHz–300 MHz 1.8 V VDD 1.8 V and 1.5 V I/O Features • Simultaneous Read and Write SigmaQuad Interface • JEDEC-standard pinout and package	Original	GS8342Q08/09/18/36E-300/250/200/167 165-Bump 165-bump, 144Mb GS8342Q08E-250I GS8342Q08E-200I GS8342Q08\E-167I 165-Pin	PDF
GS8180D18D-100 Abstract: GS8180D18D-133 GS8180D18D-167 GS8180D18D-167I GS8180D18D-200 GS8180D18D-200I GS8180D18D-250 GS8180D18D-250I Text: GS8180D18D-250/200/167/133/100 250 MHz–100 MHz 1.8 V VDD 1.8 V or 1.5 V I/O 18Mb Burst of 4 SigmaQuad SRAM 165-Bump BGA Commercial Temp Industrial Temp Features • Simultaneous Read and Write SigmaQuad Interface • JEDEC-standard pinout and package	Original	GS8180D18D-250/200/167/133/100 165-Bump 165-bump, 144Mb 165-in GS8180D18GD-167I 165-Pin GS8180D18GD-133I GS8180D18GD-100I GS8180D18D-100 GS8180D18D-133 GS8180D18D-167 GS8180D18D-167I GS8180D18D-200 GS8180D18D-200I GS8180D18D-250 GS8180D18D-250I	PDF
Untitled Abstract: No abstract text available Text: Preliminary GS8342S08/18/36E-400/300/250/200/167 36Mb Burst of 2 DDR SigmaSIO-II SRAM 165-Bump BGA Commercial Temp Industrial Temp 167 MHz–400 MHz 1.8 V VDD 1.8 V and 1.5 V I/O Features • Simultaneous Read and Write SigmaSIO Interface • JEDEC-standard pinout and package	Original	GS8342S08/18/36E-400/300/250/200/167 165-Bump 165-bump, 144Mb Sigma0/200/167 GS8342S08E-167I 165-Pin GS834x36E-300T. 8342Sxx	PDF
GS8662Q36E-250I Abstract: GS8662Q18E gs8662q18e250 Text: Preliminary GS8662Q08/09/18/36E-300/250/200/167 72Mb SigmaQuad-II Burst of 2 SRAM 165-Bump BGA Commercial Temp Industrial Temp 167 MHz–300 MHz 1.8 V VDD 1.8 V and 1.5 V I/O Features • Simultaneous Read and Write SigmaQuad Interface • JEDEC-standard pinout and package	Original	GS8662Q08/09/18/36E-300/250/200/167 165-Bump 165-bump, 144Mb GS8662Q08E-200I GS8662Q08E-167I 165-Pin GS8662x36E-200T. GS8662Q36E-250I GS8662Q18E gs8662q18e250	PDF

Untitled Abstract: No abstract text available Text: Preliminary GS8342R08/18/36E-400/300/250/200/167 36Mb SigmaCIO DDR-II Burst of 4 SRAM 165-Bump BGA Commercial Temp Industrial Temp 167 MHz–400 MHz 1.8 V VDD 1.8 V and 1.5 V I/O Features • Simultaneous Read and Write SigmaCIO Interface • Common I/O bus	Original	GS8342R08/18/36E-400/300/250/200/167 165-Bump 165-bump, 144Mb GS834x36E-300T. GS8342Rxx	PDF
Untitled Abstract: No abstract text available Text: Preliminary GS8182S18/36D-330/300/250/200/167/133 18Mb Σ2x1B2 DDR SigmaSIO-II SRAM 165-Bump BGA Commercial Temp Industrial Temp 133 MHz–330 MHz 1.8 V VDD 1.8 V and 1.5 V I/O Features • Simultaneous Read and Write SigmaQuad Interface • JEDEC-standard pinout and package	Original	GS8182S18/36D-330/300/250/200/167/133 165-Bump 165-bump, 144Mb 165-Pin	PDF
ECHO schematic diagrams Abstract: flip chip bga 0,8 mm Text: Preliminary GS8170DW18/36/72C-333/300/250 18Mb Σ1x1 Double Late Write SigmaRAM SRAM 209-Bump BGA Commercial Temp Industrial Temp 250 MHz–333 MHz 1.8 V VDD 1.8 V and 1.5 V I/O Features • Double Late Write mode • JEDEC-standard SigmaRAM™ pinout and package	Original	GS8170DW18/36/72C-333/300/250 209-Bump 209-bump, 8170DW18 ECHO schematic diagrams flip chip bga 0,8 mm	PDF
GS8182S36D-167 Abstract: GS8182S36D-200 GS8182S36D-250 GS8182S36D-300 GS8182S36D-333I Text: Preliminary GS8182S18/36D-333/300/250/200/167 18Mb Burst of 2 DDR SigmaSIO-II SRAM 165-Bump BGA Commercial Temp Industrial Temp 167 MHz–333 MHz 1.8 V VDD 1.8 V and 1.5 V I/O Features • Simultaneous Read and Write SigmaQuad Interface • JEDEC-standard pinout and package	Original	GS8182S18/36D-333/300/250/200/167 165-Bump 165-bump, 8182Sxx 333MHz GS8182S36D-167 GS8182S36D-200 GS8182S36D-250 GS8182S36D-300 GS8182S36D-333I	PDF
Untitled Abstract: No abstract text available Text: Preliminary GS8182S18/36D-333/300/250/200/167 18Mb Σ2x1B2 DDR SigmaSIO-II SRAM 165-Bump BGA Commercial Temp Industrial Temp 167 MHz–333 MHz 1.8 V VDD 1.8 V and 1.5 V I/O Features • Simultaneous Read and Write SigmaQuad Interface • JEDEC-standard pinout and package	Original	GS8182S18/36D-333/300/250/200/167 165-Bump 165-bump, 144Mb GS818x36D-300T. 8182Sxx 333MHz	PDF
GS8182S36D-200 Abstract: GS8182S36D-250 GS8182S36D-300 Text: Preliminary GS8182S18/36D-333/300/250/200/167 18Mb Σ2x1B2 DDR SigmaSIO-II SRAM 165-Bump BGA Commercial Temp Industrial Temp 167 MHz–333 MHz 1.8 V VDD 1.8 V and 1.5 V I/O Features • Simultaneous Read and Write SigmaQuad Interface • JEDEC-standard pinout and package	Original	GS8182S18/36D-333/300/250/200/167 165-Bump 165-bump, 8D-167I 165-Pin GS818x36D-300T. 8182Sxx 333MHz GS8182S36D-200 GS8182S36D-250 GS8182S36D-300	PDF
U8 100E Abstract: BGA2002 ECHO schematic diagrams GS8170DD36C-300 GS8170DD36C-333 Text: Preliminary GS8170DD18/36C-333/300/250 18Mb Σ1x2Lp Double Data Rate SigmaRAM SRAM 209-Bump BGA Commercial Temp Industrial Temp 250 MHz–333 MHz 1.8 V VDD 1.8 V and 1.5 V I/O Features • Double Data Rate Read and Write mode • JEDEC-standard SigmaRAM™ pinout and package	Original	GS8170DD18/36C-333/300/250 209-Bump 209-bump, 209-Pin GS8170DD18C-333I GS8170DD18C-300I GS8170DD18C-250I U8 100E BGA2002 ECHO schematic diagrams GS8170DD36C-300 GS8170DD36C-333	PDF
72C33 Abstract: DSA00180016.txt Text: Preliminary GS8170LW18/36/72C-333/300/250 18Mb Σ1x1 Late Write SigmaRAM SRAM 209-Bump BGA Commercial Temp Industrial Temp 250 MHz–333 MHz 1.8 V VDD 1.8 V and 1.5 V I/O Features • Late Write mode • User-configurable pipeline and flow through operation	Original	GS8170LW18/36/72C-333/300/250 209-Bump 8170LW18 72C33 DSA00180016.txt	PDF
GS8182S18 Abstract: GS8182S18D-167 GS8182S18D-200 GS8182S18D-250 GS8182S18D-250I GS8182S18D-267 Text: GS8182S18D-267/250/200/167 18Mb Burst of 2 DDR SigmaSIO-II SRAM 165-Bump BGA Commercial Temp Industrial Temp 267 MHz–167 MHz 1.8 V VDD 1.8 V and 1.5 V I/O Features • Simultaneous Read and Write SigmaQuad Interface • JEDEC-standard pinout and package	Original	GS8182S18D-267/250/200/167 165-Bump 165-bump, 8182Sxx GS8182S18 GS8182S18D-167 GS8182S18D-200 GS8182S18D-250 GS8182S18D-250I GS8182S18D-267	PDF
GS8180DV18D-100 Abstract: GS8180DV18D-133 GS8180DV18D-167 GS8180DV18D-200 GS8180DV18D-250 Text: GS8180DV18D-250/200/167/133/100 250 MHz–100 MHz 2.5 V VDD 1.8 V or 1.5 V I/O 18Mb Burst of 4 SigmaQuad SRAM 165-Bump BGA Commercial Temp Industrial Temp Features • Simultaneous Read and Write SigmaQuad Interface • JEDEC-standard pinout and package	Original	GS8180DV18D-250/200/167/133/100 165-Bump 165-bump, 144Mb 165-BGA GS8180DV18GD-167I 165-Pin GS8180DV18GD-133I GS8180DV18GD-100I GS8180DV18D-100 GS8180DV18D-133 GS8180DV18D-167 GS8180DV18D-200 GS8180DV18D-250	PDF

1.8 MM PITCH BGA Search Results

1.8 MM PITCH BGA Result Highlights (5)

1.8 MM PITCH BGA Datasheets Context Search

gs8182d18d200

Untitled

CYUSB301X

Untitled

GS818

Untitled

k2333

Untitled

Untitled

ECHO schematic diagrams

Untitled

GS8180D18D-100

Untitled

GS8662Q36E-250I

Untitled

Untitled

ECHO schematic diagrams

GS8182S36D-167

Untitled

GS8182S36D-200

U8 100E

72C33

GS8182S18

GS8180DV18D-100