Please enter a valid full or partial manufacturer part number with a minimum of 3 letters or numbers

    12 BITS SUBTRACTOR Search Results

    12 BITS SUBTRACTOR Result Highlights (5)

    Part ECAD Model Manufacturer Description Download Buy
    SNJ5480J Rochester Electronics LLC Adder/Subtractor, TTL, CDIP14, Visit Rochester Electronics LLC Buy
    SNJ54H183J Rochester Electronics LLC Adder/Subtractor, TTL/H/L Series, 1-Bit, TTL, CDIP14 Visit Rochester Electronics LLC Buy
    100182FC Rochester Electronics LLC Adder/Subtractor, 100K Series, 1-Bit, ECL, CQFP24, CERPAK-24 Visit Rochester Electronics LLC Buy
    74ALVCH162268PF Renesas Electronics Corporation 12BIT/24BIT REG. BUS EXCH Visit Renesas Electronics Corporation
    ALVCH162268U Renesas Electronics Corporation 12BIT/24BIT REG. BUS EXCH Visit Renesas Electronics Corporation

    12 BITS SUBTRACTOR Datasheets Context Search

    Catalog Datasheet MFG & Type Document Tags PDF

    8 bit sequential multiplier VERILOG

    Abstract: rtax4000 cdse full subtractor RTAX2000D 41-BIT
    Text: SmartGen Hard Multiplier Adder/Subtractor v1.0 Handbook Actel Corporation, Mountain View, CA 94043 2009 Actel Corporation. All rights reserved. Printed in the United States of America Part Number: 502-00-172-0 Release: May 2009 No part of this document may be copied or reproduced in any form or by any means without prior written


    Original     		PDF

    8 bit adder and subtractor

    Abstract: 8 bit subtractor subtractor 8fadd 12 bits subtractor full adder full subtractor application application of full subtractor
    Text: Application Brief 126 Subtractors in FLEX 8000 Devices Subtractors in FLEX 8000 Devices May 1994, ver. 1 Summary Files using the techniques described in this application brief are available from the Altera BBS at 408 954-0104 in the following self-extracting file:


    Original     		PDF

    8fadd

    Abstract: subtractor 8 bit adder and subtractor full subtractor full subtractor applications 8 bit subtractor application of full subtractor
    Text: Application Brief 126 Subtractors in FLEX 8000 Devices Subtractors in FLEX 8000 Devices May 1994, ver. 1 Summa ry Files using the techniques described in this application brief are available from the Altera BBS at 408 954-0104 in the following self-extracting file:


    Original     		PDF

    REG168

    Abstract: "Overflow detection" FULL SUBTRACTOR using 41 MUX
    Text: PDSP16318/16318A PDSP16318/PDSP16318A Complex Accumulator Advance Information Supersedes version DS3708 - 2.4 September 1996 DS3708 - 3.1 November 1998 The PDSP16318/A contains two independent 20-bit Adder/Subtractors combined with accumulator registers and


    Original     		PDSP16318/16318A PDSP16318/PDSP16318A DS3708 PDSP16318/A 20-bit 20MHz PDSP16318As PDSP16112A GC100 REG168 "Overflow detection" FULL SUBTRACTOR using 41 MUX PDF

    ALU of 4 bit adder and subtractor

    Abstract: circuit diagram of full subtractor circuit 16-bit adder DS3708 GC100 PDSP1601 PDSP16112 PDSP16112A PDSP16116 PDSP16330
    Text: PDSP16318/16318A PDSP16318/PDSP16318A Complex Accumulator Advance Information Supersedes version DS3708 - 2.4 September 1996 DS3708 - 3.1 November 1998 The PDSP16318/A contains two independent 20-bit Adder/Subtractors combined with accumulator registers and


    Original     		PDSP16318/16318A PDSP16318/PDSP16318A DS3708 PDSP16318/A 20-bit 20MHz PDSP16318As PDSP16112A GC100 ALU of 4 bit adder and subtractor circuit diagram of full subtractor circuit 16-bit adder GC100 PDSP1601 PDSP16112 PDSP16112A PDSP16116 PDSP16330 PDF

    FULL SUBTRACTOR using 41 MUX

    Abstract: ALU of 4 bit adder and subtractor DS3708 circuit diagram of full subtractor circuit GC100 PDSP1601 PDSP16112 PDSP16112A PDSP16116 PDSP16330
    Text: PDSP16318/16318A PDSP16318/PDSP16318A Complex Accumulator Advance Information Supersedes version DS3708 - 2.4 September 1996 DS3708 - 3.1 November 1998 The PDSP16318/A contains two independent 20-bit Adder/Subtractors combined with accumulator registers and


    Original     		PDSP16318/16318A PDSP16318/PDSP16318A DS3708 PDSP16318/A 20-bit 20MHz PDSP16318As PDSP16112A GC100 FULL SUBTRACTOR using 41 MUX ALU of 4 bit adder and subtractor circuit diagram of full subtractor circuit GC100 PDSP1601 PDSP16112 PDSP16112A PDSP16116 PDSP16330 PDF

    ALU of 4 bit adder and subtractor

    Abstract: FULL SUBTRACTOR using 41 MUX subtractor GC100 PDSP1601 PDSP16112 PDSP16112A PDSP16116 PDSP16330 DS3708
    Text: PDSP16318/16318A PDSP16318/PDSP16318A Complex Accumulator Advance Information Supersedes version DS3708 - 2.4 September 1996 DS3708 - 3.1 November 1998 The PDSP16318/A contains two independent 20-bit Adder/Subtractors combined with accumulator registers and


    Original     		PDSP16318/16318A PDSP16318/PDSP16318A DS3708 PDSP16318/A 20-bit 20MHz PDSP16318As PDSP16112A GC100 ALU of 4 bit adder and subtractor FULL SUBTRACTOR using 41 MUX subtractor GC100 PDSP1601 PDSP16112 PDSP16112A PDSP16116 PDSP16330 PDF

    FULL SUBTRACTOR using 41 MUX

    Abstract: "Overflow detection"
    Text: PDSP16318/16318A PDSP16318/PDSP16318A Complex Accumulator Advance Information Supersedes version DS3708 - 2.4 September 1996 DS3708 - 3.1 November 1998 The PDSP16318/A contains two independent 20-bit Adder/Subtractors combined with accumulator registers and


    Original     		PDSP16318/16318A PDSP16318/PDSP16318A DS3708 PDSP16318/A 20-bit 20MHz PDSP16318As PDSP16112A GC100 FULL SUBTRACTOR using 41 MUX "Overflow detection" PDF

    AHDL adder subtractor

    Abstract: 8 bit adder and subtractor adder-subtractor design AHDL subtractor 8 bit adder floating point verilog 4-bit AHDL adder subtractor AHDL adder
    Text: fp_add_sub Floating-Point Adder/Subtractor January 1996, ver. 1 Features Functional Specification 2 • ■ ■ ■ ■ General Description fp_add_sub reference design implementing a floating-point adder/subtractor Parameterized mantissa and exponent widths


    Original     		PDF

    FULL SUBTRACTOR using 41 MUX

    Abstract: ALU of 4 bit adder and subtractor "Overflow detection"
    Text: PDSP16318/16318A PDSP16318/PDSP16318A Advance Information Complex Accumulator Advance Information DS3708 The PDSP16318 contains two independent 20-bit Adder/ Subtractors combined with accumulator registers and shift structures. The four port architecture permits full 20MHz


    Original     		PDSP16318/16318A PDSP16318/PDSP16318A DS3708 PDSP16318 20-bit 20MHz PDSP16318As PDSP16112A PDSP16318A/B0/AC FULL SUBTRACTOR using 41 MUX ALU of 4 bit adder and subtractor "Overflow detection" PDF

    FULL SUBTRACTOR using 41 MUX

    Abstract: "Overflow detection"
    Text: PDSP16318 MC PDSP16318 MC Complex Accumulator DS3761 ISSUE 2.1 The PDSP16318 contains two independent 20-bit Adder/ Subtractors combined with accumulator registers and shift structures. The four port architecture permits full 10MHz throughout in FFT and filter applications.


    Original     		PDSP16318 DS3761 20-bit 10MHz PDSP16318s PDSP16112A 100ns GC100 FULL SUBTRACTOR using 41 MUX "Overflow detection" PDF

    DS3708

    Abstract: PDSP16112 PDSP16112A PDSP16318 FULL SUBTRACTOR using 41 MUX asi mux ALU of 4 bit adder and subtractor "Overflow detection" TTL ALU of 4 bit adder and subtractor CMOS Full Adder
    Text: PDSP16318/16318A PDSP16318/PDSP16318A Advance Information Complex Accumulator Advance Information DS3708 The PDSP16318 contains two independent 20-bit Adder/ Subtractors combined with accumulator registers and shift structures. The four port architecture permits full 20MHz


    Original     		PDSP16318/16318A PDSP16318/PDSP16318A DS3708 PDSP16318 20-bit 20MHz PDSP16318As PDSP16112A PDSP16318A/B0/AC 20MHz DS3708 PDSP16112 PDSP16112A FULL SUBTRACTOR using 41 MUX asi mux ALU of 4 bit adder and subtractor "Overflow detection" TTL ALU of 4 bit adder and subtractor CMOS Full Adder PDF

    "Overflow detection"

    Abstract: FULL SUBTRACTOR using 41 MUX
    Text: PDSP16318 MC PDSP16318 MC Complex Accumulator DS3761 ISSUE 2.1 The PDSP16318 contains two independent 20-bit Adder/ Subtractors combined with accumulator registers and shift structures. The four port architecture permits full 10MHz throughout in FFT and filter applications.


    Original     		PDSP16318 DS3761 20-bit 10MHz PDSP16318s PDSP16112A 100ns GC100 "Overflow detection" FULL SUBTRACTOR using 41 MUX PDF

    FULL SUBTRACTOR using 41 MUX

    Abstract: PDSP16112 ALU of 4 bit adder and subtractor GC100 PDSP16112A PDSP16318 "Overflow detection"
    Text: PDSP16318 MC PDSP16318 MC Complex Accumulator DS3761 ISSUE 2.1 The PDSP16318 contains two independent 20-bit Adder/ Subtractors combined with accumulator registers and shift structures. The four port architecture permits full 10MHz throughout in FFT and filter applications.


    Original     		PDSP16318 DS3761 20-bit 10MHz PDSP16318s PDSP16112A 100ns GC100 FULL SUBTRACTOR using 41 MUX PDSP16112 ALU of 4 bit adder and subtractor GC100 PDSP16112A "Overflow detection" PDF

    half adder ttl

    Abstract: column-major TMC2311 adder-subtractor design TMC2312 DIN11 TMC2220 TMC2250 TMC2272 "Huffman coding"
    Text: TMC2311 C M O S Fast Cosine Transform Processor 12 Bits, 15 Million Pixels Per Second The TMC2311, a high-speed algorithm specific processor, computes the one or tw o dimensional forward discrete cosine transform DCT of an 8 or 8x8 point array of contiguous 9-bit data or the inverse DCT of 12-bit data.


    OCR Scan     		TMC2311 TMC2311, 12-bit TMC2311 2311R1C2 half adder ttl column-major adder-subtractor design TMC2312 DIN11 TMC2220 TMC2250 TMC2272 "Huffman coding" PDF

    c2311

    Abstract: No abstract text available
    Text: TMC2311 TMC2311 CMOS Fast Cosine Transform Processor 12 Bits, 15 Million Pixels Per Second Description Features The TM C2311, a high-speed algorithm specific ♦ processor, computes the one or two dimensional forward discrete cosine transform DCT of an 8 or 8x8 point array


    OCR Scan     		TMC2311 C2311, 12-bit C2311 TMC2311R1C TMC2311R1C1 TMC2311R1C2 2311R1C 2311R1C1 PDF

    Untitled

    Abstract: No abstract text available
    Text: TMC2311 TMC2311 CMOS Fast Cosine IVansform Processor 12 Bits, 15 Million Pixels Per Second Description Features The TM C2311, a high-speed algorithm specific ♦ Stand alone execution of 8-point forward or inverse ♦ cosine transform Continuous 8x8-point 2-D DCTs every 4.48 ¿is


    OCR Scan     		TMC2311 C2311, 12-bit TMC2311R1C 2311R1C TMC2311R1C1 2311R1C1 TMC2311R1C2 2311R1C2 PDF

    Untitled

    Abstract: No abstract text available
    Text: AMI S2811 A M ERICAN M ICR O SY ST EM S, INC. SIGNAL PROCESSING PERIPHERAL General Description Features The S2811 Sign al Processing Peripheral S P P is a high speed special purpose arithm etic processor w ith on-chip R O M , R A M , m ultiplier, adder/subtractor, accum ulator


    OCR Scan     		S2811 S2811 12-bit 256x17) PDF

    Untitled

    Abstract: No abstract text available
    Text: GEC P L E S S E Y DS3706 • 2.4 PDSP16318/PDSP16318 A COMPLEX ACCUMULATOR Supersedes version in December 1993 D igital Video & Video D igital Signal Processing 1C Handbook, HB3923-1 The PDSP16318 contains two independent 20-bit Adder/ Subtractors combined with accumulator registers and shift


    OCR Scan     		DS3706 PDSP16318/PDSP16318 HB3923-1) PDSP16318 20-bit 20MHz PDSP16318As PDSP16112A PDSP16318/13618A PDSP16318A/B0/AC PDF

    Untitled

    Abstract: No abstract text available
    Text: W tflGEC PLESSEY P R E L IM IN A R Y IN F O R M A T IO N DS3708 - 2.0 PDSP16318/PDSP16318A COMPLEX ACCUMULATOR The PDSP16318 contains two independent 20-bit Adder/ Subtractors combined with accumulator registers and shift structures. The four port architecture permits full 20MHz


    OCR Scan     		DS3708 PDSP16318/PDSP16318A PDSP16318 20-bit 20MHz PDSP16318As PDSP16112A 256ps. PDSP16318/13618A PDSP16318/C0/AC PDF

    Untitled

    Abstract: No abstract text available
    Text: PDSP16318/PDSP16318A M ITEL Complex Accumulator SE M IC O N D U C T O R Supersedes version DS3708 - 2.4 Advance Inform ation Septem ber 1996 DS3708 -3 .1 Novem ber 1998 The PDSP16318/A contains two independent 20-bit Adder/Subtractors combined with accumulator registers and


    OCR Scan     		PDSP16318/PDSP16318A DS3708 PDSP16318/A 20-bit 20MHz 16318Ascom P16112A 256ns. 20MHz PDF

    Untitled

    Abstract: No abstract text available
    Text: M IT E L PDSP16318 MC SE M IC O N D U C T O R Complex Accumulator DS3761 - 2.1 Supersedes April 1993 version, DS3761 - 1.2 Novem ber 1998 The PDSP16318 contains two independent 20-bit Adder/ Subtractors combined with accumulator registers and shift structures. The four port architecture permits full 10MHz


    OCR Scan     		PDSP16318 DS3761 20-bit 10MHz PDSP16318s PDSP16112A 100ns 512ns. PDF

    PDSP1640

    Abstract: No abstract text available
    Text: PLESSEY SEMICONDUCTORS 12E & • 7220513 OQlQOfla 5 ■ N O T R EC O M M ENDED FOR N EW DESIGNS. PLEASE USE PDSP16318/A PLESSEY Sem iconductors , — ,«« n. , PDSP16316/PDSP16316A COMPLEX ACCUMULATOR The PDSP16316 contains two independent 20-bit Adder/Subtractors combined with accumulator registers


    OCR Scan     		PDSP16318/A PDSP16316 20-bit 20MHz PDSP16316As PDSP16112A 256jus. PDSP16316/PDSP16316A 120-PIN PDSP1640 PDF

    "Overflow detection"

    Abstract: No abstract text available
    Text: PDSP16318/PDSP16318A M ITEL Complex Accumulator SEMICONDUCTOR Supersedes version DS3708 - 2.4 Advance Inform ation Septem ber 1996 DS3708 - 3.1 November 1998 The PDSP16318/A contains two independent 20-bit Adder/Subtractors combined with accumulator registers and


    OCR Scan     		PDSP16318/PDSP16318A DS3708 PDSP16318/A 20-bit 20MHz DSP16318As PDSP16112A 16-bit "Overflow detection" PDF