CY37128P84-125JI
Abstract: No abstract text available
Text: 256 PRELIMINARY CY37128 UltraLogic 128-Macrocell ISR™ CPLD Features • • • • • • • • • • 128 macrocells in eight logic blocks • In-System Reprogrammable™ ISR™ — JTAG-compliant on-board programming — Design changes don’t cause pinout changes
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CY37128
128-Macrocell
84-Lead
CY37128P84-125JI
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CY37128
Abstract: CY37128V CLCC 84 CY37128P100-167AC O64i CY37128P84-125JI
Text: 7256 PRELIMINARY CY37128 UltraLogic 128-Macrocell ISR™ CPLD Features • • • • • • • • • • • 128 macrocells in eight logic blocks • In-System Reprogrammable ISR™ — JTAG-compliant on-board programming — Design changes don’t cause pinout changes
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CY37128
128-Macrocell
CY37128
CY37128V
CLCC 84
CY37128P100-167AC
O64i
CY37128P84-125JI
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CY37128P84-125JI
Abstract: Ultra37000TM CY3600 37128P100
Text: fax id: 6146 1Ult ra371 28 PRELIMINARY Ultra37128 UltraLogic 128-Macrocell ISR™ CPLD Features • High speed — fMAX = 167 MHz • 128 macrocells in eight logic blocks • In-System Reprogrammable ISR™ — JTAG compliant on board programming — tPD = 6.5 ns
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ra371
Ultra37128
128-Macrocell
84-pin
100-pin
160-pin
FLASH374i/5i
CY37128P84-125JI
Ultra37000TM
CY3600
37128P100
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CY37128
Abstract: CY37128V CLCC 84 CY37128P84-125JI
Text: Ultra37256 Back PRELIMINARY CY37128 UltraLogic 128-Macrocell ISR™ CPLD Features • • • • • • • • • • • 128 macrocells in eight logic blocks • In-System Reprogrammable ISR™ — JTAG-compliant on-board programming — Design changes don’t cause pinout changes
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Ultra37256
CY37128
128-Macrocell
CY37128
CY37128V
CLCC 84
CY37128P84-125JI
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cy37128
Abstract: CY37128P160-125AC CY37128V CY7C375 CY37128P84-125JI cy3700
Text: = m m m !Æ '^ r ^ r : c Q CY3 7 1 2 8 PR £um A ^Y UltraLogic 128-Macrocell ISR™ CPLD — tco = 4.0 ns Features • • • • • • • • • • • 128 macrocells in eight logic blocks • In-System Reprogrammable™ ISR™ — JTAG-compliant on-board programming
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CY37128
128-Macrocell
cy37128
CY37128P160-125AC
CY37128V
CY7C375
CY37128P84-125JI
cy3700
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SY100E167
Abstract: SY100E167JC SY10E167 SY10E167JC
Text: This Material C o p y r i g h t e d B y Its R e s p e c t i v e M a n u f a c t u r e r SY10E167 SY100E167 SEM IC O N D U C TO R TRUTH TABLE SEL Data H a L b D C E L E C T R IC A L C H A R A C T E R IS T IC S V ee = VEE Min. to VEE (Max.); VCC = Vcco = GND
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SY10E167
SY100E167
SY10E167JC
J28-1
SY100E167JC
T0013Ã
SY100E167
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SY100E167
Abstract: SY10E167 SY10E167JC
Text: * 6-BIT 2:1 MUX-REGISTER SYNERGY SY10E167 SY100E167 S E M IC O N D U C T O R DESCRIPTION FEATURES • 1000MHz min. operating frequency ■ Extended 100E V e e range of -4.2V to -5.5V ■ 800ps max. clock to output ■ Single-ended outputs ■ Asynchronous Master Reset
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SY10E167
SY100E167
1000MHz
800ps
75KC2
MC10E/100E167
SY10/100E167
SY10E167JC
J28-1
SY10E167JCTR
SY100E167
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J281C
Abstract: No abstract text available
Text: * SYNERGY ! û fr 1 8 7 b-BIT 2 1 M Ü X• R E G iS f ER -Y 1HOE 1B7 S E M IC O N D U C T O R FEATURES • 1000MHz min. operating frequency ■ Extended 100E V ee range of -4.2V to -5.5V ■ 800ps max. clock to output ■ Single-ended outputs ■ Asynchronous Master Reset
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1000MHz
800ps
MC10E/100E167
28-pin
10/100E
SY10E
167JC
J281C
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CY37128P160-125AC
Abstract: cpld internal CY3600 CY37128P100-167AC Ultra37128 CY37128P84-125JI
Text: fax id: 6146 : : M : : IP *: ; M : : Ultra37128 .PRELIMINARY W CYPRESS UltraLogic 128-Macrocell ISR™ CPLD Features High speed f|\/lAX = 167 M Hz • 128 m a cro c ells in eig h t logic blocks — t PD = 6.5 ns • In-S ystem R e p ro g ra m m ab le IS R ™
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Ultra37128
128-Macrocell
CY37128P160-125AC
cpld internal
CY3600
CY37128P100-167AC
Ultra37128
CY37128P84-125JI
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CY3600
Abstract: tI11J CY37128P84-125JI
Text: fax id: 6146 ÆÊ PRELIMINARY F T V f S T “ ¡T * &*• risaliiJF ;UI Flmßbö Ultra37128 U ltraLogic 128-Macrocell IS R ™ CPLD H ig h s p e e d Features — • 128 m a c ro c e lls in e ig h t lo g ic b lo c k s f MAX = 167 M H z — t PD = 6.5 ns
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Ultra37128
128-Macrocell
CY3600
tI11J
CY37128P84-125JI
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