DS16
Abstract: MC8051M36 MC8051M36L-7R5VI
Text: MC8051M36 36-Mbit: 1Mx36 MOSYS Symmetric Pipelined Burst SRAM The MC8051M36 is packaged in a standard 100 lead LQFP. Lowest Power The MC8051M36 affords systems dramatic power savings due to the benefits of its proprietary MoSys technology. Making it ideal for convection cooled applications, as well as
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Original
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MC8051M36
36-Mbit:
1Mx36
MC8051M36
DS16
MC8051M36L-7R5VI
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PDF
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FullFlex36
Abstract: CYDXXS36V18 400 OHM RESISTOR DQ67
Text: CYDXXS72V18 CYDXXS36V18 CYDXXS18V18 FullFlex Synchronous SDR Dual Port SRAM FullFlex™ Synchronous SDR Dual Port SRAM Features Functional Description • True dual port memory enables simultaneous access the shared array from each port ■ Synchronous pipelined operation with single data rate SDR
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Original
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CYDXXS72V18
CYDXXS36V18
CYDXXS18V18
18-Mbit,
36-Mbit
FullFlex72
72-bit
FullFlex36
400 OHM RESISTOR
DQ67
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PDF
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FullFlex36
Abstract: No abstract text available
Text: CYDXXS72V18 CYDXXS36V18 CYDXXS18V18 FullFlex Synchronous SDR Dual Port SRAM FullFlex™ Synchronous SDR Dual Port SRAM Features Functional Description • True dual port memory enables simultaneous access the shared array from each port ■ Synchronous pipelined operation with single data rate SDR
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Original
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CYDXXS72V18
CYDXXS36V18
CYDXXS18V18
72-bit
18-Mbit,
36-Mbit
FullFlex36
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PDF
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FullFlex36
Abstract: CYD09S36V18 CYD18S18V18 CYD18S36V18
Text: FullFlex FullFlexTM Synchronous SDR Dual Port SRAM FullFlex Synchronous SDR Dual Port SRAM Features Functional Description • True dual port memory enables simultaneous access the shared array from each port ■ Synchronous pipelined operation with single data rate SDR
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Original
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72-bit
18-Mbit,
36-Mbit
FullFlex36
CYD09S36V18
CYD18S18V18
CYD18S36V18
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PDF
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FullFlex36
Abstract: No abstract text available
Text: CYDXXS72V18 CYDXXS36V18 CYDXXS18V18 FullFlex Synchronous SDR Dual Port SRAM FullFlex™ Synchronous SDR Dual Port SRAM Features Functional Description • True dual port memory enables simultaneous access the shared array from each port ■ Synchronous pipelined operation with single data rate SDR
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Original
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CYDXXS72V18
CYDXXS36V18
CYDXXS18V18
18-Mbit,
36-Mbit
FullFlex72
72-bit
FullFlex36
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PDF
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FullFlex36
Abstract: No abstract text available
Text: CYDXXS72V18 CYDXXS36V18 CYDXXS18V18 FullFlex Synchronous SDR Dual Port SRAM FullFlex™ Synchronous SDR Dual Port SRAM Features Functional Description • True dual port memory enables simultaneous access the shared array from each port ■ Synchronous pipelined operation with single data rate SDR
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Original
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CYDXXS72V18
CYDXXS36V18
CYDXXS18V18
18-Mbit,
36-Mbit
FullFlex72
72-bit
FullFlex36
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PDF
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FullFlex36
Abstract: No abstract text available
Text: CYDXXS72V18 CYDXXS36V18 CYDXXS18V18 FullFlex Synchronous SDR Dual Port SRAM FullFlex™ Synchronous SDR Dual Port SRAM Features Functional Description • True dual port memory enables simultaneous access the shared array from each port ■ Synchronous pipelined operation with single data rate SDR
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Original
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CYDXXS72V18
CYDXXS36V18
CYDXXS18V18
72-bit
484-ball
256-ball
FullFlex36
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PDF
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FullFlex36
Abstract: DQ67L CYD18S72V18
Text: FullFlex FullFlexTM Synchronous SDR Dual Port SRAM FullFlex Synchronous SDR Dual Port SRAM Features Functional Description • True dual port memory enables simultaneous access to the shared array from each port ■ Synchronous pipelined operation with single data rate SDR
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Original
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18-Mbit,
36-Mbit
FullFlex72
72-bit
FullFlex36
DQ67L
CYD18S72V18
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PDF
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Untitled
Abstract: No abstract text available
Text: CY7C1444AV33 36-Mbit 1 M x 36 Pipelined DCD Sync SRAM 36-Mbit (1 M × 36) Pipelined DCD Sync SRAM Features Functional Description • Supports bus operation up to 167 MHz ■ Available speed grade is 167 MHz ■ Registered inputs and outputs for pipelined operation
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Original
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CY7C1444AV33
36-Mbit
CY7C1444AV33
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PDF
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Untitled
Abstract: No abstract text available
Text: CY7C1444AV33 36-Mbit 1 M x 36 Pipelined DCD Sync SRAM 36-Mbit (1 M × 36) Pipelined DCD Sync SRAM Functional Description Features • Supports bus operation up to 167 MHz ■ Available speed grade is 167 MHz ■ Registered inputs and outputs for pipelined operation
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Original
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CY7C1444AV33
36-Mbit
167-MHz
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PDF
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Untitled
Abstract: No abstract text available
Text: CY7C1444AV33 36-Mbit 1 M x 36 Pipelined DCD Sync SRAM 36-Mbit (1 M × 36) Pipelined DCD Sync SRAM Features Functional Description • Supports bus operation up to 250 MHz ■ Available speed grades are 250 MHz and 167 MHz ■ Registered inputs and outputs for pipelined operation
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Original
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CY7C1444AV33
36-Mbit
CY7C1444AV33
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PDF
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Untitled
Abstract: No abstract text available
Text: CY7C1444AV33 36-Mbit 1 M x 36 Pipelined DCD Sync SRAM 36-Mbit (1 M × 36) Pipelined DCD Sync SRAM Features Functional Description • Supports bus operation up to 167 MHz ■ Available speed grade is 167 MHz ■ Registered inputs and outputs for pipelined operation
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Original
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CY7C1444AV33
36-Mbit
CY7C1444AV33
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PDF
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FullFlex36
Abstract: CYD04S36V18 CYD09S36V18 CYD18S18V18 CYD18S36V18
Text: FullFlex FullFlexTM Synchronous SDR Dual Port SRAM FullFlex Synchronous SDR Dual Port SRAM Features Functional Description • True dual port memory enables simultaneous access to the shared array from each port ■ Synchronous pipelined operation with single data rate SDR
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Original
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72-bit
484-ball
256-ball
FullFlex72
36-Mbit:
CYD36S72V18)
18-Mbit:
CYD18ation
FullFlex36
CYD04S36V18
CYD09S36V18
CYD18S18V18
CYD18S36V18
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PDF
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Untitled
Abstract: No abstract text available
Text: CY7C1440AV33 36-Mbit 1 M x 36 Pipelined Sync SRAM 36-Mbit (1 M × 36) Pipelined Sync SRAM Features Functional Description • Supports bus operation up to 250 MHz ■ Available speed grades are 250 and 167 MHz ■ Registered inputs and outputs for pipelined operation
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Original
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CY7C1440AV33
36-Mbit
CY7C1440AV33
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PDF
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Untitled
Abstract: No abstract text available
Text: CY7C1440AV33 36-Mbit 1 M x 36 Pipelined Sync SRAM 36-Mbit (1 M × 36) Pipelined Sync SRAM Features Functional Description • Supports bus operation up to 250 MHz ■ Available speed grades are 250 and 167 MHz ■ Registered inputs and outputs for pipelined operation
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Original
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CY7C1440AV33
36-Mbit
CY7C1440AV33
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PDF
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Untitled
Abstract: No abstract text available
Text: CY7C1461AV33 CY7C1463AV33 36-Mbit 1 M x 36/2 M × 18 Flow-Through SRAM with NoBL Architecture 36-Mbit (1 M × 36/2 M × 18) Flow-Through SRAM with NoBL™ Architecture Features Functional Description • No Bus Latency™ (NoBL™) architecture eliminates dead
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Original
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CY7C1461AV33
CY7C1463AV33
36-Mbit
CY7C1461AV33/CY7C1463AV33
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PDF
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Untitled
Abstract: No abstract text available
Text: CY7C1461AV33 CY7C1463AV33 36-Mbit 1 M x 36/2 M × 18 Flow-Through SRAM with NoBL Architecture 36-Mbit (1 M × 36/2 M × 18) Flow-Through SRAM with NoBL™ Architecture Features Functional Description • No Bus Latency™ (NoBL™) architecture eliminates dead
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Original
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CY7C1461AV33
CY7C1463AV33
36-Mbit
CY7C1461AV33/CY7C1463AV33
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PDF
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Untitled
Abstract: No abstract text available
Text: CY7C1461AV33 CY7C1463AV33 36-Mbit 1 M x 36/2 M × 18 Flow-Through SRAM with NoBL Architecture 36-Mbit (1 M × 36/2 M × 18) Flow-Through SRAM with NoBL™ Architecture Features Functional Description • No Bus Latency™ (NoBL™) architecture eliminates dead
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Original
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CY7C1461AV33
CY7C1463AV33
36-Mbit
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PDF
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Untitled
Abstract: No abstract text available
Text: CY7C1460AV25 CY7C1462AV25 36-Mbit 1 M x 36/2 M × 18 Pipelined SRAM with NoBL Architecture 36-Mbit (1 M × 36/2 M × 18) Pipelined SRAM with NoBL™ Architecture Features Functional Description • Pin-compatible and functionally equivalent to ZBT™
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Original
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CY7C1460AV25
CY7C1462AV25
36-Mbit
CY7C1460AV25/CY7C1462AV25
CY7C14ponents
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PDF
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Untitled
Abstract: No abstract text available
Text: CY7C1460AV33 CY7C1462AV33 36-Mbit 1 M x 36/2 M × 18 Pipelined SRAM with NoBL Architecture 36-Mbit (1 M × 36/2 M × 18/512 K × 72) Pipelined SRAM with NoBL™ Architecture Features Functional Description • Pin compatible and functionally equivalent to ZBT
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Original
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CY7C1460AV33
CY7C1462AV33
36-Mbit
CY7C1460AV33/CY7C1462AV33
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PDF
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Untitled
Abstract: No abstract text available
Text: CY7C1460AV33 CY7C1462AV33 36-Mbit 1 M x 36/2 M × 18 Pipelined SRAM with NoBL Architecture 36-Mbit (1 M × 36/2 M × 18) Pipelined SRAM with NoBL™ Architecture Features Functional Description • Pin compatible and functionally equivalent to ZBT ■
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Original
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CY7C1460AV33
CY7C1462AV33
36-Mbit
CY7C1460AV33/CY7C1462AV33
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PDF
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Untitled
Abstract: No abstract text available
Text: CY7C1460AV33 CY7C1462AV33 36-Mbit 1 M x 36/2 M × 18 Pipelined SRAM with NoBL Architecture 36-Mbit (1 M × 36/2 M × 18) Pipelined SRAM with NoBL™ Architecture Features Functional Description • Pin compatible and functionally equivalent to ZBT ■
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Original
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CY7C1460AV33
CY7C1462AV33
36-Mbit
CY7C1460AV33/CY7C1462AV33
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PDF
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Untitled
Abstract: No abstract text available
Text: CY7C1444AV33 CY7C1445AV33 36-Mbit 1 M x 36/2 M × 18 Pipelined DCD Sync SRAM 36-Mbit (1 M × 36/2 M × 18) Pipelined DCD Sync SRAM Features Functional Description[1] • Supports bus operation up to 250 MHz ■ Available speed grades are 250, 200, and 167 MHz
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Original
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CY7C1444AV33
CY7C1445AV33
36-Mbit
CY7C1444AV33/CY7C1445AV33
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PDF
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MOSYS
Abstract: MC8051M36 MC8051M36L-7R5VI 1.8V SRAM
Text: ♦ MC8051M36 36-Mbit: 1Mx36 M o Sys * Symmetric Pipelined Burst SRAM • High Performance • 133-200MHz Speed grades • 3-1-1-1 Burst Read • 3-1-1-1 Burst Write • 3-1-1-1-1-1-1-1. pipelined operation lu • Symm etric Pipeline • No bus turnaround latency allowing 100% bus efficiency
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OCR Scan
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MC8051M36
36-Mbit:
1Mx36
133-200MHz
MC8051M36
MOSYS
MC8051M36L-7R5VI
1.8V SRAM
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PDF
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