Untitled
Abstract: No abstract text available
Text: SMJ27C210 1 048576-BIT UV ERASABLE PROGRAMMABLE READ-ONLY MEMORY SM G S028A — MARCH 19B8 — REVISED N O VEM BER 1990 J Package Top View Single 5-V Power Supply Operationally Compatible With Existing Megabit EPROMs 40-Pln Dual-In-line Package All Inputs and Outputs Fully TTL
|
OCR Scan
|
SMJ27C210
048576-BIT
S028A
40-Pln
SMJ27C210-12
SMJ27C210-15
SMJ27C210-17
SMJ27C210-20
SMJ27C210-25
|
PDF
|
LC1 D33
Abstract: No abstract text available
Text: a Prelim inary Advanced Micro Devices A m 2110 ISDN Terminal Adapter Circuit ITAC DISTINCTIVE CHARACTERISTICS • Universal adapter for ISDN R reference point ■ ■ Support of async and sync Interfaces: X.21, X.21 bis, V.24, RS232C Automatic calling/answering with on-chip
|
OCR Scan
|
RS232C
Am2110
LC1 D33
|
PDF
|
MD80C31BH
Abstract: MD80C31BH/B M80C31BH
Text: M80C51BH/M80C31BH CMOS SINGLE-CHIP 8-BIT MICROCOMPUTER Military m M80C31BH—Control Oriented CPU with • ■ ■ ■ ■ ■ ■ 64K Program Memory Space a High Performance CHMOS Process _ Boolean Processor S Interrupt Sources B Programmable Serial Port
|
OCR Scan
|
M80C51BH/M80C31BH
M80C31BHâ
M80C51BHâ
M80C31BH
16-Bit
40-Pln
44-Pln
44-Pln
MD80C31BH
MD80C31BH/B
|
PDF
|
Untitled
Abstract: No abstract text available
Text: P R is y iif iiO K iÆ in r in ie l VE28F008 8 MBIT (1 MBIT x 8 FLASH MEMORY • High-Density Symmetrically Blocked Architecture — Sixteen 64 Kbyte Blocks Very High-Performance Read — 95 ns Maximum Access Time ■ Avionics Temperature Range 40°C to + 125°C
|
OCR Scan
|
VE28F008
-40-Lead
4AEL17S
40-Pln
28F008SA-L
AP-359
28F008SA
AP-360
|
PDF
|
Untitled
Abstract: No abstract text available
Text: Preliminary b q 4 0 2 4 / b q 4 0 2 4 Y BENCHMARQ 128KX16 Nonvolatile SRAM Features General Description > D ata retention in the absence of The CMOS bq4024 is a nonvolatile 2,097,152-bit static RAM organized as 131,072 words by 16 bits. The in te g ra l co n tro l circ u itry an d
|
OCR Scan
|
128KX16
bq4024
152-bit
40-pin
10-year
|
PDF
|
BQ4025
Abstract: bq4025Y
Text: bq4025/bq4025Y BENCHMARQ 256KX16 Nonvolatile SRAM Features General Description > Data retention in the absence of power The CMOS bq4025 is a nonvolatile 4,194,304-bit static RAM organized as 262,144 w ords by 16 b its . The integral control circuitry and lithium
|
OCR Scan
|
bq4025/bq4025Y
256KX16
bq4025
304-bit
D0037CH
bq4025Y
|
PDF
|
Optocouplers for rs232 ttl
Abstract: maxim rs232 isolated MAX252 8 pin MAX252BCHL MAX 232 internal block diagram MAX252 MAX252BEHL MAX252ACHL MAX252AEHL E118032
Text: yi/iyjxi>ui 19-2370; Rev 2; 10/91 C om plete, +5V-Pow ered, Is o la te d , D ual R S -232 T ran sceiver M odule Features ♦ Is o la te d D ata In te rfa c e ♦ N o E x te rn a l C o m p o n e n ts ♦ S in g le + 5 V S u p p ly ♦ 5 0 n W L o w -P o w e r S h u td o w n
|
OCR Scan
|
RS-232
MAX252
MAX252A
130Vrms
1260Vrms
1520Vrms
Optocouplers for rs232 ttl
maxim rs232 isolated
MAX252 8 pin
MAX252BCHL
MAX 232 internal block diagram
MAX252BEHL
MAX252ACHL
MAX252AEHL
E118032
|
PDF
|
HA 12058
Abstract: No abstract text available
Text: Preliminary Product Specification Z89300 S e r ie s d i g i t a l t e l e v is io n Co n t r o ller s FEATURES AND BENEFITS • Advanced TV controller 1C with sophisticated OnScreen D isplay ca p a b ility and integral VBI data
|
OCR Scan
|
Z89300
40-pin
42-pin
52-pin
16-bit
40-DIP
HA 12058
|
PDF
|
Z- FIO
Abstract: dcp 4 z Z8038
Text: Z I L O G INC 17E D T1ÖM043 DD1E0Ô3 T " T -S £ -3 3 -D 3 Z8038/Z8538 FIO FIFO Input/ Output Interface Unit October 1988 Features • 128-byte FIFO buffer provides asynchronous bidirectional CPU/CPU or CPU/peripheral interface, expandable to any width in byte
|
OCR Scan
|
Z8038/Z8538
128-byte
16-bit
68-Pin
84-Pin
Z- FIO
dcp 4 z
Z8038
|
PDF
|
GG41
Abstract: No abstract text available
Text: April 1993 Edition 2.1 FUJITSU DATA S H E E T M B 8 1 8 2 5 1 -70/-80 2097,152 Bits 262,144 x 8 Bits Multi-port CMOS Dynamic RAM The Fujitsu MB818251 is a fully decoded dual port CMOS Dynamic RAM (DRAM) organized as 262,144 words by 8 bits dynamic RAM port and 512 words by 8 bits serial
|
OCR Scan
|
MB818251
400mil
40-pin
475mil
44-pin
MB818251
GG41
|
PDF
|
Untitled
Abstract: No abstract text available
Text: LOGIC DEVICES INC 2kE D • SSbSTQS 0D01É11 T ■ _ _ T - Ÿ S - 0 7 LMU08/LMU8U 8 x 8-bit Parallel Multiplier FEATURES Q 35 ns Worst-Case Multiply Time Q Low Power CMOS Technology □ LMU08 Replaces TRW MPY008H
|
OCR Scan
|
LMU08/LMU8U
LMU08
MPY008H
MPY08HU
LMU08)
MIL-STD883,
40-pin
44-pin
|
PDF
|
Z86e4012
Abstract: Z86E40 SXGR 86E4012
Text: ZIL06 INC 30E D B =1=104043 D017b24 -1. » Z I L - T -4 9 -1 9 -0 7 P r o d u c t S p e c if ic a t io n Z8ÌE40 CMOS Z8 OTP CCP MICROCONTROLLER FEATURES • 8-bit CMOS microcontroller ■ Digital inputs CMOS levels, Schmitt triggered
|
OCR Scan
|
l7b24
T-49-19-07
44-pin
40-Pln,
0G17bfl0
286E40
40-Pin
Z86e4012
Z86E40
SXGR
86E4012
|
PDF
|
7006C
Abstract: TOA8
Text: '- / Ú - FUJITSU S3E L TD 3 7 4 cl75b G D 0 3 3 S S D .2 3 ^ /7 TOb » F C A J June 1992 Edition 1.0 FUJITSU DATA SHEET M B 8 1 4 2 6 0 A -70/-80/-10 CMOS 256K X 16 BIT FAST PAGE MODE DYNAMIC RAM CMOS 262,144 x 16 bit Fast Page Mode Dynamic RAM The Fujitsu MB814260A is a fully decoded CMOS Dynamic RAM DRAM that contains 4,194,304
|
OCR Scan
|
MB814260A
16-bit
16-bits
MB814260A-70/-80/-10
7006C
TOA8
|
PDF
|
AM9513
Abstract: BCD DIVISION e purse AM9513CC AM9513DM AM9513 counter bft 5f g1
Text: A m 9 5 1 3 y m System T im ing C o n tro lle r ^ Advanced M icro Devices H g a w 'W A dvanced MOS/LSI I DISTINCTIVE CHARACTERISTICS GENERAL DESCRIPTION • Five independent 16-bit counters The Am9513 System Timing Controller is an LSI circuit designed to service many types of courting, sequencing and timing appli
|
OCR Scan
|
Am9513
16-bit
40-pin
1009c
MIL-STD-883
40-Pln
AM9513
BCD DIVISION
e purse
AM9513CC
AM9513DM
AM9513 counter
bft 5f g1
|
PDF
|
|
|
TI15J
Abstract: 88C681 68C681 EJ34
Text: ËXÂRCÔRPÏÏ Ï E | 3422klS D0 0 4 2 2 'i D | 0 'f^ 7J - 3 7 -0f ' X R -8 8 C 6 8 1/6 8 C 6 8 1 E X 4R CMOS Dual Channel UART DUART GENERAL DESCRIPTION =. Normal, Autoecho, Local Loopback, and Remote Loopback Modes Multi-Function 16-Bit Counter/Timer
|
OCR Scan
|
3422klS
XR88C681
Z8000,
XR-68C681
RS232C
XR-1488
XR-1489A
XR-1488N
TI15J
88C681
68C681
EJ34
|
PDF
|
TDA 2025
Abstract: Z80 CPU PHYSICAL DIMENSIONS LCC tda 2015 Z84C0006CMB TDA 2025 chip z84c0006 cpu Z80 CPU DIMENSIONS centrifuge machine for acceleration 84C0006 zilog z80 dynamic ram Application
Text: ZILOG 9984043 ZILO G INC 03 DËJ 4 0 4 3 03E IN C IL ITA R Y 000044 2 5 | ~ 08442 ¿S, roduct S p ecification l : April 1988 Z84C00 CMOS Z80 CPU Central Processing Unit T - H q - n - o i FEATURES • The CMOS Z80 combines the high performance of the
|
OCR Scan
|
Z84C00
000fi4b5
40-Pln
Z84C0006CME
Z84C0006CMB
84C00
TDA 2025
Z80 CPU PHYSICAL DIMENSIONS LCC
tda 2015
Z84C0006CMB
TDA 2025 chip
z84c0006 cpu
Z80 CPU DIMENSIONS
centrifuge machine for acceleration
84C0006
zilog z80 dynamic ram Application
|
PDF
|
SCB2675
Abstract: SCB2675BC8N40 SCB2675CC5A44 signetics 2670 SCB2675BC5A44
Text: SCB2675 Color/Monochrome Attributes Controller CMAC Product Specification Microprocessor Products PIN CONFIGURATIONS DESCRIPTION FEATURES The Signetics SCB2675 Color/Mono chrome Attributes Controller (CMAC) is a bipolar LSI device designed for CRT terminals and display systems that em
|
OCR Scan
|
SCB2675
SCB2675
SCB2675BC8N40
SCB2675CC5A44
signetics 2670
SCB2675BC5A44
|
PDF
|
Untitled
Abstract: No abstract text available
Text: 1^ 1 W NEC Electronics Inc. pPD424260A/L, 42S4260A/L 262,144 X 16-Bit Dynamic CMOS RAM Preliminary Information Description The /L/PD424260A/L and /JPD42S4260A/L are fast-page dynamic RAMs organized as 262,144 words by 16 bits and designed to operate from a single power supply:
|
OCR Scan
|
pPD424260A/L,
42S4260A/L
16-Bit
/L/PD424260A/L
/JPD42S4260A/L
24260A
424260L
42S4260A
42S4260L
|
PDF
|
Untitled
Abstract: No abstract text available
Text: D P V 128X 16A H IG H S PEED 1 2 8 K X 16 U V E P R O M P G A M O D U L E PRELIM IN ARY D ESCRIPTIO N: The DPV128X16A is a 40-pin Pin Grid Array PG A consisting of two 128K X 8 U V EP R O M devices in ceramic LCC packages surface mounted on a co-fired ceramic substrate with matched thermal coefficients.
|
OCR Scan
|
DPV128X16A
40-pin
250ns
V128X16
120ns
150ns
170ns
200ns
-t-85
|
PDF
|
73M450-IP
Abstract: 73M450 73M450L-IP
Text: SSI 73M450L/1450/2450 ¿ é m s v s k m Universal Asynchronous Receiver/Transmitter s A TDK G rou p /C om p any January 1993 DESCRIPTION FEATURES The SSI 73M450L is a Universal Asynchronous Receiver/Transmitter UART circuit which is pin- and function-compatible with industry-standard 16C450type UARTs. It is primarily used in the interface be
|
OCR Scan
|
73M450L/1450/2450
73M450L
16C450type
40-pin
44-pin
73M1450
73M2450
28-pin
73M450L.
73M450-IP
73M450
73M450L-IP
|
PDF
|
Untitled
Abstract: No abstract text available
Text: SAMSUNG E L E C T R O N I C S INC b?E ]> • 7Tb414e KM616513 DG17bE4 251 H S r i G K CMOS SRAM 32,768 WORD X 16 BIT FEATURES GENERAL DESCRIPTION • Fast Access Time 15, 17, 20, 25ns max. • Low Power Dissipation Standby (TTL) : 50mA(max.) (CMOS): 1 mA(max.)
|
OCR Scan
|
7Tb414e
KM616513
DG17bE4
KM616513
288-bit
400mil)
|
PDF
|
Untitled
Abstract: No abstract text available
Text: LPR520/521 ht vu t -, iNi u h K jh a ii h FEATURES DESCRIPTION □ Fou r 16-bit R egisters □ Im plem ents D ouble 2-Stage Pipe line or Sin g le 4-Stage P ipeline Register □ H old, Shift, and Load Instructions □ Separate D ata In and Data O ut Pins
|
OCR Scan
|
LPR520/521
16-bit
LPR520
LPR521
T29FCT520/
IDT29FCT521
Am29521
LPR521PC25
|
PDF
|
1000-01P
Abstract: d0ji
Text: iÿ > S L G E P ro d u c t S p e c ific a tio n Z8536 CIO Counter/Timer and Parallel I/O Unit September 1988 Faaturas G aaarol DMcription • Two independent 8-bit, double-buffered, bidirectional I/O ports plus a 4-bit special-purpose I/O port. I/O ports feature programmable polarity,
|
OCR Scan
|
Z8536
IEEE-488)
Z0853606PSC
1000-01P
d0ji
|
PDF
|
NEC d70108 V20
Abstract: d70108 nec d70108 nec V20 70108 V20 70108 PD70108 bytes and string manipulation of 8086 tfkd 340
Text: //PD70108 V20 8/16-Bit Microprocessor: High-Performance, CMOS NEC D escriptio n O rd erin g In fo rm a tio n T h e //P D 7 0 1 0 8 (V20 ) is a C M O S 16-bit m icroprocessor with internal 16-bit architecture and an 8-b it external data bus. T h e /iP D 7 0 1 0 8 instruction set is a superset of
|
OCR Scan
|
uPD70108
16-bit
uPD701
/PD70108
theyuPD70116
//PD70108
8/16-Bit
NEC d70108 V20
d70108
nec d70108
nec V20 70108
V20 70108
PD70108
bytes and string manipulation of 8086
tfkd 340
|
PDF
|
