Untitled
Abstract: No abstract text available
Text: LTM8028 36VIN, UltraFast, Low Output Noise 5A µModule Regulator Features Description High Performance 5A Linear Regulator with Switching Step-Down Converter for High Efficiency n Digitally Programmable V OUT: 0.8V to 1.8V n Input Voltage Range: 6V to 36V
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LTM8028
36VIN,
100kHz)
LTM8048
300mA
LTM4615
LTM4620
8028fb
com/LTM8028
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PDF
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Untitled
Abstract: No abstract text available
Text: LTM8028 36VIN, UltraFast, Low Output Noise 5A µModule Regulator Features Description High Performance 5A Linear Regulator with Switching Step-Down Converter for High Efficiency n Digitally Programmable V OUT: 0.8V to 1.8V n Input Voltage Range: 6V to 36V
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Original
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LTM8028
36VIN,
100kHz)
LTM8048
300mA
LTM4615
LTM4620
8028fa
com/LTM8028
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PDF
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Untitled
Abstract: No abstract text available
Text: CY7C1361A CY7C1363A 256K x 36/512K x 18 Synchronous Flow-Thru Burst SRAM Features • • • • • • • • • • • • • • • • • • Fast access times: 6.0, 6.5, 7.0, and 8.0 ns Fast clock speed: 150, 133, 117, and 100 MHz Fast OE access times: 3.5 ns and 4.0 ns
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Original
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CY7C1361A
CY7C1363A
36/512K
CY7C1361A/CY7C1363A
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PDF
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CY7C1361A-100AC
Abstract: CY7C1361A CY7C1363A A101
Text: CY7C1361A CY7C1363A 256K x 36/512K x 18 Synchronous Flow-Thru Burst SRAM Features • • • • • • • • • • • • • • • • • • Fast access times: 6.0, 6.5, 7.0, and 8.0 ns Fast clock speed: 150, 133, 117, and 100 MHz Fast OE access times: 3.5 ns and 4.0 ns
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Original
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CY7C1361A
CY7C1363A
36/512K
contro61A/CY7C1363A
CY7C1361A-100AC
CY7C1361A
CY7C1363A
A101
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PDF
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EP2AGX65
Abstract: EP2AGX45 EP2AGX260 EP2AGX190 EP2AGX125 358PIN EP2AGX45 ubga 780-Pin
Text: 7. External Memory Interfaces in Arria II GX Devices AIIGX51007-3.0 This chapter describes the hardware features in Arria II GX devices that facilitate high-speed memory interfacing for the double data rate DDR memory standard including delay-locked loops (DLLs). Memory interfaces also use I/O features such as
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Original
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AIIGX51007-3
EP2AGX65
EP2AGX45
EP2AGX260
EP2AGX190
EP2AGX125
358PIN
EP2AGX45 ubga
780-Pin
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PDF
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EP2AGX65
Abstract: EP2AGX190 EP2AGX260 UniPHY EP2AGX125 EP2AGX45 358p
Text: 7. External Memory Interfaces in Arria II GX Devices AIIGX51007-2.0 Altera Arria® II GX FPGAs provide an efficient architecture to quickly and easily fit wide external memory interfaces with their small modular I/O bank structure. The I/Os are designed to provide flexible and high-performance support for existing and
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Original
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AIIGX51007-2
EP2AGX65
EP2AGX190
EP2AGX260
UniPHY
EP2AGX125
EP2AGX45
358p
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PDF
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C5440
Abstract: TPS543xx TMS320C5510 DSK tms320C5402 C5000 rj11 plug to 3.5mm TPS70758 C5402 BGA 144 C55X
Text: TMS320C5000 : The Personal DSP World’s Most Power-Efficient DSPs Platform Update August 2000 Mark Mattson C5000™ Product Marketing Manager C5000 Personal DSP C5000 Platform Update Agenda !Market Positioning !Market Acceptance !Targeted Applications
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Original
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TMS320C5000
C5000TM
C5000
C2000TM
C6000TM
C55xTM
C64xTM
C28xTM
C5440
TPS543xx
TMS320C5510
DSK tms320C5402
rj11 plug to 3.5mm
TPS70758
C5402
BGA 144
C55X
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PDF
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CY7C1357A
Abstract: GVT71512ZB18
Text: 1CY7C1357A PRELIMINARY CY7C1355A/GVT71256ZB36 CY7C1357A/GVT71512ZB18 256Kx36/512Kx18 Flow-Thru SRAM with NoBL Architecture Features • Zero Bus Latency, no dead cycles between write and read cycles • Fast clock speed: 133, 117, and 100 MHz • Fast access time: 6.5, 7.0, 7.5, and 8.0 ns
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Original
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1CY7C1357A
CY7C1355A/GVT71256ZB36
CY7C1357A/GVT71512ZB18
256Kx36/512Kx18
CY7C1357A
GVT71512ZB18
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PDF
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EP4SGX180
Abstract: EP4SGX360 EP4SGX290 EP4SE230 EP4SE360 EP4SE530 EP4SGX70 1152-pin
Text: 7. External Memory Interfaces in Stratix IV Devices SIV51007-3.1 This chapter describes external memory interfaces available with the Stratix IV device family and that family’s silicon capability to support external memory interfaces. To support the level of system bandwidth achievable with Altera ®
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Original
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SIV51007-3
EP4SGX180
EP4SGX360
EP4SGX290
EP4SE230
EP4SE360
EP4SE530
EP4SGX70
1152-pin
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PDF
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Untitled
Abstract: No abstract text available
Text: CY7C1354A/GVT71256ZC36 CY7C1356A/GVT71512ZC18 256K x 36/512K x 18 Pipelined SRAM with NoBL Architecture Features • Zero Bus Latency, no dead cycles between Write and Read cycles • Fast clock speed: 200, 166, 133, 100 MHz • Fast access time: 3.2, 3.6, 4.2, 5.0 ns
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CY7C1354A/GVT71256ZC36
CY7C1356A/GVT71512ZC18
36/512K
operation1354A/GVT71256ZC36
CY7C1354A/GVT71256ZC36
CY7C1356A/GVT71512ZC18
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PDF
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LTM4612
Abstract: sr 2262 AN-110 EN55022B LTM4612EV LTM4612MPV GRM32ER71H106K 5V-to-36V schematic diagram converter input 12v to 24v 4a ltm4612ivpbf
Text: Features Complete Low EMI Switch Mode Power Supply n EN55022 Class B Compliant n Wide Input Voltage Range: 5V to 36V n 3.3V to 15V Output Voltage Range n 5A DC, 7A Peak Output Current n Low Input and Output Referred Noise n Output Voltage Tracking and Margining
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EN55022
LTM4612MPV)
LTM4627
20VIN,
LTM4618
26VIN,
LTM8033
EN55022B
36VIN,
4612fb
LTM4612
sr 2262
AN-110
LTM4612EV
LTM4612MPV
GRM32ER71H106K
5V-to-36V
schematic diagram converter input 12v to 24v 4a
ltm4612ivpbf
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PDF
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Untitled
Abstract: No abstract text available
Text: LTM8001 36VIN, 5A µModule Regulator with 5-Output Configurable LDO Array Features Description Complete Step-Down Switch Mode Power Supply with Configurable Array of Five LDOs n Step-Down Switching Power Supply – Adjustable 10% Accurate Output Current Limit
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Original
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LTM8001
36VIN,
100Hz
16-Bit
LTC2974
LTC3880
8001fc
com/LTM8001
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PDF
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Untitled
Abstract: No abstract text available
Text: LTM4612 EN55022B Compliant 36VIN, 15VOUT, 5A, DC/DC µModule Regulator DESCRIPTION FEATURES n n n n n n n n n n n n n n n n n Complete Low EMI Switch Mode Power Supply EN55022 Class B Compliant Wide Input Voltage Range: 5V to 36V 3.3V to 15V Output Voltage Range
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LTM4612
EN55022B
36VIN,
15VOUT,
EN55022
LTM4612MPV)
LTM4627
20VIN,
LTM4618
26VIN,
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PDF
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gal16v8d programming algorithm
Abstract: gal programming algorithm vantis jtag schematic 1 of 8 selector 96 L 2 GAL16V8D LATTICE 3000 SERIES cpld PALCE610H-XX ISPGDX160A GAL22V10D
Text: Lattice and Vantis Product Selector Guide February 2000 Universe of Programmable Solutions Introduction Lattice and Vantis 3.3V and 2.5V ISP CPLD Families Lattice and Vantis. The companies that gave the world ISP and took you Beyond Performance now bring you their combined
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Original
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ISPpPAC10
28-pin
ispPAC20-01JI
ispPAC20
44-pin
PAC-SYSTEM10
ispPAC10
PAC-SYSTEM20
gal16v8d programming algorithm
gal programming algorithm
vantis jtag schematic
1 of 8 selector
96 L 2
GAL16V8D
LATTICE 3000 SERIES cpld
PALCE610H-XX
ISPGDX160A
GAL22V10D
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PDF
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CY7C1360A
Abstract: CY7C1362A
Text: CY7C1360A CY7C1362A 256K x 36/512K x 18 Synchronous Pipelined Burst SRAM Features • • • • • • • • • • • • • • • • • • Fast access times: 2.5 ns, 3.0 ns, and 3.5 ns Fast clock speed: 225, 200, 166, and 150 MHz Fast OE access times: 2.5 ns, 3.0 ns, and 3.5 ns
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Original
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CY7C1360A
CY7C1362A
36/512K
CY7C1360A
CY7C1362A
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PDF
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Untitled
Abstract: No abstract text available
Text: CY7C1360A CY7C1362A 256K x 36/512K x 18 Synchronous Pipelined Burst SRAM Features • • • • • • • • • • • • • • • • • • Fast access times: 2.5 ns, 3.0 ns, and 3.5 ns Fast clock speed: 225, 200, 166, and 150 MHz Fast OE access times: 2.5 ns, 3.0 ns, and 3.5 ns
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Original
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CY7C1360A
CY7C1362A
36/512K
CY7C1360A
CY7C1362A
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PDF
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4612 mosfet
Abstract: GRM32ER71H106K LTM4612 LTM4612V 24v 12v 10A regulator LTM4612IV 624k ap 4612 ceramic capacitor E5 LTM4608
Text: LTM4612 Ultralow Noise 36VIN, 15VOUT, 5A, DC/DC µModule Regulator Description Features Complete Low EMI Switch Mode Power Supply CISPR 22 Class B Compliant Wide Input Voltage Range: 5V to 36V 5A DC, 7A Peak Output Current 3.3V to 15V Output Voltage Range
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Original
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LTM4612
36VIN,
15VOUT,
LTM4612MPV)
LTM4608A
LTM8020
LTM8021
LTM8022/LTM8023
4612fa
4612 mosfet
GRM32ER71H106K
LTM4612
LTM4612V
24v 12v 10A regulator
LTM4612IV
624k
ap 4612
ceramic capacitor E5
LTM4608
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PDF
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GRM32ER71H106K
Abstract: ceramic capacitor E5 schematic diagram converter input 12v to 24v 4a LTM4612MPV LTM4612V 4612 fet LTM4612IV 24v 12v 2A regulator ceramic capacitor marking E5 LTM4603-1
Text: LTM4612 Ultralow Noise 36VIN, 15VOUT, 5A, DC/DC µModule DESCRIPTION FEATURES n n n n n n n n n n n n n n n n n n Complete Low EMI Switch Mode Power Supply CISPR 22 Class B Compliant Wide Input Voltage Range: 5V to 36V 5A DC, 7A Peak Output Current 3.3V to 15V Output Voltage Range
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Original
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LTM4612
36VIN,
15VOUT,
LTM4612MPV)
LTM4608A
LTM8020
LTM8021
LTM8022/LTM8023
GRM32ER71H106K
ceramic capacitor E5
schematic diagram converter input 12v to 24v 4a
LTM4612MPV
LTM4612V
4612 fet
LTM4612IV
24v 12v 2A regulator
ceramic capacitor marking E5
LTM4603-1
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PDF
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CY7C1356A
Abstract: GVT71512ZC18
Text: CY7C1354A/GVT71256ZC36 CY7C1356A/GVT71512ZC18 256K x 36/512K x 18 Pipelined SRAM with NoBL Architecture Features • Zero Bus Latency™, no dead cycles between Write and Read cycles • Fast clock speed: 200, 166, 133, 100 MHz • Fast access time: 3.2, 3.6, 4.2, 5.0 ns
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Original
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CY7C1354A/GVT71256ZC36
CY7C1356A/GVT71512ZC18
36/512K
BG119)
CY7C1356A
GVT71512ZC18
|
PDF
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CY7C1362A
Abstract: GVT71512D18
Text: CY7C1360A/GVT71256D36 CY7C1362A/GVT71512D18 256K x 36/512K x 18 Synchronous Pipelined Burst SRAM Features • • • • • • • • • • • • • • • • • • Fast access times: 2.5 ns, 3.0 ns, and 3.5 ns Fast clock speed: 225, 200, 166, and 150 MHz
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Original
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CY7C1360A/GVT71256D36
CY7C1362A/GVT71512D18
36/512K
CY7C1360A/GVT71256D36
CY7C1362A
GVT71512D18
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PDF
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CY7C1360A
Abstract: CY7C1362A 1362A
Text: CY7C1360A CY7C1362A 256K x 36/512K x 18 Synchronous Pipelined Burst SRAM Features • • • • • • • • • • • • • • • • • • Fast access times: 2.5 ns, 3.0 ns, and 3.5 ns Fast clock speed: 225, 200, 166, and 150 MHz Fast OE access times: 2.5 ns, 3.0 ns, and 3.5 ns
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Original
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CY7C1360A
CY7C1362A
36/512K
CY7C1360A
CY7C1362A
1362A
|
PDF
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Untitled
Abstract: No abstract text available
Text: MR4A08B FEATURES 2M x 8 MRAM Memory • +3.3 Volt power supply • Fast 35 ns read/write cycle • SRAM compatible timing • Unlimited read & write endurance • Data always non-volatile for >20-years at temperature • RoHS-compliant small footprint BGA and TSOP2 packages
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MR4A08B
20-years
AEC-Q100
MR4A08B
216-bit
EST00356
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PDF
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MR4A08BMYS35
Abstract: No abstract text available
Text: MR4A08B FEATURES 2M x 8 MRAM Memory • +3.3 Volt power supply • Fast 35 ns read/write cycle • SRAM compatible timing • Unlimited read & write endurance • Data always non-volatile for >20-years at temperature • RoHS-compliant small footprint BGA and TSOP2 packages
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Original
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MR4A08B
20-years
AEC-Q100
MR4A08B
216-bit
EST00356
MR4A08BMYS35
|
PDF
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GVT71256ZC36B-7.5
Abstract: CY7C1356A-100AC CY7C1356A GVT71512ZC18
Text: PRELIMINARY CY7C1354A/GVT71256ZC36 CY7C1356A/GVT71512ZC18 256Kx36/512Kx18 Pipelined SRAM with NoBL Architecture Features • Zero Bus Latency, no dead cycles between write and read cycles • Fast clock speed: 200, 166, 133, and 100 MHz • Fast access time: 3.2, 3.6, 4.2, 5.0 ns
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Original
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CY7C1354A/GVT71256ZC36
CY7C1356A/GVT71512ZC18
256Kx36/512Kx18
GVT71256ZC36B-7.5
CY7C1356A-100AC
CY7C1356A
GVT71512ZC18
|
PDF
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