Contextual Info: v2 .1  Axcelerator Family FPGAs u e Leading-Edge Performance • • • • – 350+ MHz System Performance 500+ MHz Internal Performance High-Performance Embedded FIFOs 700Mb/s LVDS Capable I/Os Specifications • • • • • Up to 2 Million Equivalent System Gates

RDRAM CONCURRENT

Abstract: samsung concurrent rdram KM49RC2H-A66 km49rc2h-a60 km-48 concurrent RDRAM 72 KM49RC2H
Contextual Info: Preliminary Concurrent RDRAM KM48 9 RC2H 16/18Mbit R D R A M 2M X 8/9bit Concurrent RAMBUS DRAM Revision 0.7 February 1998 Rev. 0.7 (Feb. 1998) Preliminary Concurrent RDRAM KM48(9)RC2H Revision History Revision 0.5 (October 1997) - Preliminary • . Changed Peak TrasferRate from 700Mbps to 667Mbps. (page 1)

Axcelerator FPGAs

Abstract: AX125 AX2000 CQ208 CS180 PQ208 M33 thermal fuse AK 1022 Axcelerator Family FPGAs
Contextual Info: v2 .1  Axcelerator Family FPGAs u e Leading-Edge Performance • • • • – 350+ MHz System Performance 500+ MHz Internal Performance High-Performance Embedded FIFOs 700Mb/s LVDS Capable I/Os Specifications • • • • • Up to 2 Million Equivalent System Gates

AF367

Abstract: AK 1022 IC KA 2312 P2272 AX1000
Contextual Info: Advanced v1.6  Axcelerator Family FPGAs Le adi n g- E dg e P e rfo r ma nc e • • • • 350+ MHz System Performance 500+ MHZ Internal Performance High-Performance Embedded FIFOs 700Mb/s LVDS Capable I/Os S pe ci fi c at i on s • • • • • Up to 2 Million Equivalent System Gates

g5134

Contextual Info: v2.0  Axcelerator Family FPGAs Le adi n g- E dg e P e rfo r ma nc e • • • • 350+ MHz System Performance 500+ MHz Internal Performance High-Performance Embedded FIFOs 700Mb/s LVDS Capable I/Os S pe ci fi c at i on s • • • • • Up to 2 Million Equivalent System Gates

Contextual Info: Advanced v1.6  Axcelerator Family FPGAs Le adi n g- E dg e P e rfo r ma nc e • • • • 350+ MHz System Performance 500+ MHZ Internal Performance High-Performance Embedded FIFOs 700Mb/s LVDS Capable I/Os S pe ci fi c at i on s • • • • • Up to 2 Million Equivalent System Gates

7443003

Contextual Info: CD-R O PERATIN G PLAY TEM P. —25~+70°C O PERATIN G (REC O RD ) TEM P. -5~+55°C '. . IF É ^ r u p ié ' 1 f è ìl~ 2 4 f t Ä Ì T ' X - A - 7 ' f K U > v I B i l ì S J t f t j f c "Super wide range" design assure of writing at all speed (1x to 24x)

Contextual Info: Changing how documents are managed Reduce faxing and copying costs Protect and preserve documents Easily share and access paper documents Space saving compact design One button scanning to PDF Color Duplex 15 pages per minute! Included to work with Microsoft

NT5DS4M32EF-25

Abstract: NT5DS4M32EF-28 NT5DS4M32EF-33 NT5DS4M32EF-4
Contextual Info: NT5DS4M32EF 4Mx32 Double Data Rate SDRAM 128Mbit DDR SDRAM 1M x 32Bit x 4 Banks Double Data Rate Synchronous RAM With Bi-directional Data Strobe and DLL 144-Ball FBGA Nanya Technology Corp. NTC reserves the right to change products or specification without notice.

SGMII PCIE bridge

Abstract: Scatter-Gather direct memory access SG-DMA TN1084 lvds serdes project wishbone rev. b
Contextual Info: f u l l y t e s t e d a n d i n t e r o p e r a b l e Lattice PCIe Solutions Ready-to-Use PCIe Portfolio Lattice provides designers with low cost, low power, programmable solutions that are ready-to-use right out of the box. A suite of tested and interoperable solutions is available for PCI Express,

lx64ev-3f100c

Abstract: LX64V-3F100C 3F100 5f208c LX64V-3FN100 LX64EB-5F100C LX128EV-5FN208I LX128EV-5FN208C LX64B-3FN100C LX64B-5F100C
Contextual Info: ispGDX2 Device Datasheet June 2010 Select Devices Discontinued! Product Change Notifications PCNs #09-10 has been issued to discontinue select devices in this data sheet. The original datasheet pages have not been modified and do not reflect those changes.

HY5DU561622CTP

Contextual Info: HY5DU561622CTP 256M 16Mx16 DDR SDRAM HY5DU561622CTP This document is a general product description and is subject to change without notice. Hynix Electronics does not assume any responsibility for use of circuits described. No patent licenses are implied.

MS5534AM

Abstract: DA5534 ic PRESSURE SENSOR FP4401 CAP tantal SMD "Pressure Sensor" digital output SENT protocol C6502 metal sensor interfacing with microcontroller silicon-gel-sensor MS5534
Contextual Info: MS5534A BAROMETER MODULE ♦ ♦ ♦ ♦ Integrated pressure sensor Pressure range 300-1100 mbar 15 Bit ADC 6 coefficients for a software compensation stored on-chip ♦ 3-wire serial interface ♦ 1 system clock line 32.768 kHz ♦ Low voltage / low power

HY5DS283222BF

Abstract: HY5DS283222BFP-33
Contextual Info: HY5DS283222BF P 128M(4Mx32) GDDR SDRAM HY5DS283222BF(P) This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied.

c485

Contextual Info: 19-3557; Rev 0; 2/05 27-Bit, 3MHz-to-35MHz DC-Balanced LVDS Deserializer The MAX9218 digital video serial-to-parallel converter deserializes a total of 27 bits during data and control phases. In the data phase, the LVDS serial input is converted to 18 bits of parallel video data and in the control

Contextual Info: 256M gDDR2 SDRAM K4N56163QG 256Mbit gDDR2 SDRAM Revision 1.1 April 2006 Notice INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE,

Contextual Info: 256M GDDR3 SDRAM K4J55323QG 256Mbit GDDR3 SDRAM Revision 1.2 March 2006 Notice INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE,

K4D263238G-VC33

Contextual Info: 128M GDDR SDRAM K4D263238G-GC 128Mbit GDDR SDRAM 1M x 32Bit x 4 Banks Graphic Double Data Rate Synchronous DRAM with Bi-directional Data Strobe and DLL 144-Ball FBGA Revision 1.7 February 2005 Samsung Electronics reserves the right to change products or specification without notice.

tsop-ii 66 JEDEC TRAY

Contextual Info: 128M GDDR SDRAM K4D261638F 128Mbit GDDR SDRAM Revision 1.5 March 2005 INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE,

Contextual Info: 128M DDR SDRAM K4D263238E-GC 128Mbit DDR SDRAM 1M x 32Bit x 4 Banks Double Data Rate Synchronous DRAM with Bi-directional Data Strobe and DLL 144-Ball FBGA Revision 1.2 April 2003 Samsung Electronics reserves the right to change products or specification without notice.

Contextual Info: 128M GDDR SDRAM K4D261638F 128Mbit GDDR SDRAM 2M x 16Bit x 4 Banks Graphic Double Data Rate Synchronous DRAM Revision 1.5 March 2005 Samsung Electronics reserves the right to change products or specification without notice. - 1 - Rev 1.5 Mar. 2005 128M GDDR SDRAM

MAX9217

Abstract: MAX9218 MAX9218ECM MAX9218ETM
Contextual Info: 19-3557; Rev 2; 10/05 27-Bit, 3MHz-to-35MHz DC-Balanced LVDS Deserializer The MAX9218 digital video serial-to-parallel converter deserializes a total of 27 bits during data and control phases. In the data phase, the LVDS serial input is converted to 18 bits of parallel video data and in the control

HY5DU281622ET

Abstract: HY5DU281622ET-25 HY5DU281622ET-26 HY5DU281622ET-28 HY5DU281622ET-30 HY5DU281622ET-33 HY5DU281622ET-36 HY5DU281622ET-4 HY5DU281622ET-5
Contextual Info: HY5DU281622ET 128M 8Mx16 GDDR SDRAM HY5DU281622ET This document is a general product description and is subject to change without notice. Hynix Electronics does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 0.5 / Jan. 2005

Contextual Info: LOW-COST NON-VOLATILE INFINITELY RECONFIGURABLE PLD MachXO Family Crossover Programmable Logic Devices The MachXO family of non-volatile, infinitely reconfigurable Programmable Logic Devices PLDs is designed for applications traditionally implemented using