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    74AUP Search Results

    74AUP Result Highlights (5)

    Part ECAD Model Manufacturer Description Download Buy
    74AUP1G125DCKRG4 Texas Instruments Low-Power Single Bus Buffer Gate with 3-State Output 5-SC70 -40 to 85 Visit Texas Instruments Buy
    SN74AUP1G02DBVR Texas Instruments Low-Power Single 2-Input Positive-NOR Gate 5-SOT-23 -40 to 85 Visit Texas Instruments Buy
    SN74AUP1G04DCKR Texas Instruments Low-Power Single Inverter Gate 5-SC70 -40 to 85 Visit Texas Instruments Buy
    SN74AUP1G06DBVRG4 Texas Instruments Low-Power Single Inverter Buffer/Driver with Open-Drain Outputs 5-SOT-23 -40 to 85 Visit Texas Instruments Buy
    SN74AUP1G06DRLR Texas Instruments Low-Power Single Inverter Buffer/Driver with Open-Drain Outputs 5-SOT-5X3 -40 to 85 Visit Texas Instruments Buy
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    74AUP Price and Stock

    Texas Instruments SN74AUP1G04DPWR

    IC INVERTER 1CH 1-INP 4X2SON
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    DigiKey SN74AUP1G04DPWR Cut Tape 11,969 1
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    SN74AUP1G04DPWR Digi-Reel 11,969 1
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    SN74AUP1G04DPWR Reel 9,000 3,000
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    Bristol Electronics SN74AUP1G04DPWR 9,000 9
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    Texas Instruments SN74AUP1G07DCKT

    IC BUF NON-INVERT 3.6V SC70-5
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    SN74AUP1G07DCKT Reel 10,750 250
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    Bristol Electronics SN74AUP1G07DCKT 250
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    Chip-Germany GmbH SN74AUP1G07DCKT 466
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    Win Source Electronics SN74AUP1G07DCKT 118,190
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    Nexperia 74AUP1G32GW,125

    IC GATE OR 1CH 2-INP 5TSSOP
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    Mouser Electronics 74AUP1G32GW,125 50,082
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    Newark 74AUP1G32GW,125 Cut Tape 6,670 5
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    Rochester Electronics 74AUP1G32GW,125 30,000 1
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    TTI 74AUP1G32GW,125 Reel 30,000 3,000
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    Avnet Asia 74AUP1G32GW,125 42,000 6 Weeks 15,000
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    Avnet Silica 74AUP1G32GW,125 15,000 8 Weeks 3,000
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    Chip One Stop 74AUP1G32GW,125 Cut Tape 2,750
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    New Advantage Corporation 74AUP1G32GW,125 18,000 1
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    Diodes Incorporated 74AUP1G32FW5-7

    IC GATE OR 1CH 2-INP DFN1010-6
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    Avnet Silica 74AUP1G32FW5-7 5,000 10 Weeks 5,000
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    New Advantage Corporation 74AUP1G32FW5-7 5,000 1
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    Nexperia 74AUP2G157DC,125

    IC MULTIPLEXER 1 X 2:1 8VSSOP
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    DigiKey 74AUP2G157DC,125 Digi-Reel 2,987 1
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    74AUP2G157DC,125 Cut Tape 2,987 1
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    Avnet Silica 74AUP2G157DC,125 3,000 10 Weeks 3,000
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    74AUP Datasheets (500)

    Part ECAD Model Manufacturer Description Curated Datasheet Type PDF
    74AUP1G00 Diodes SINGLE 2 INPUT POSITIVE NAND GATE Original PDF
    74AUP1G00 NXP Semiconductors Advanced ultra-low-power CMOS logic; NXP ultra-low-power CMOS logic 74AUP1G/2G/3Gxxx Original PDF
    74AUP1G00 Philips Semiconductors Low-power 2-input NAND gate Original PDF
    74AUP1G00FS3-7 Diodes Integrated Circuits (ICs) - Logic - Gates and Inverters - IC GATE NAND 1CH 2-INP DFN0808-4 Original PDF
    74AUP1G00FW4-7 Diodes SINGLE 2 INPUT POSITIVE NAND GATE Original PDF
    74AUP1G00FW5-7 Diodes Integrated Circuits (ICs) - Logic - Gates and Inverters - IC GATE NAND 1CH 2-INP DFN1010-6 Original PDF
    74AUP1G00FZ4-7 Diodes SINGLE 2 INPUT POSITIVE NAND GATE Original PDF
    74AUP1G00GF NXP Semiconductors Low-power 2-input NAND gate Original PDF
    74AUP1G00GF Philips Semiconductors Low-power 2-input NAND gate Original PDF
    74AUP1G00GF,132 NXP Semiconductors 74AUP1G00 - IC AUP/ULP/V SERIES, 2-INPUT NAND GATE, PDSO6, 1 X 1 MM, 0.50 MM HEIGHT, PLASTIC, SOT-891, SON-6, Gate Original PDF
    74AUP1G00GM NXP Semiconductors Low-power 2-input NAND gate Original PDF
    74AUP1G00GM Philips Semiconductors Low-power 2-input NAND gate Original PDF
    74AUP1G00GM,115 NXP Semiconductors 74AUP1G00 - IC AUP/ULP/V SERIES, 2-INPUT NAND GATE, PDSO6, 1 X 1.45 MM, 0.50 MM HEIGHT, PLASTIC, MO-252, SOT-886, SON-6, Gate Original PDF
    74AUP1G00GM,115 NXP Semiconductors Low-power 2-input NAND gate; Package: SOT886 (XSON6); Container: Tape reel smd Original PDF
    74AUP1G00GM,125 NXP Semiconductors 74AUP1G00GM - Low-power 2-input NAND gate, SOT886 Package, Standard Marking, Reel Pack, Reverse Original PDF
    74AUP1G00GM,132 NXP Semiconductors 74AUP1G00 - IC AUP/ULP/V SERIES, 2-INPUT NAND GATE, PDSO6, 1 X 1.45 MM, 0.50 MM HEIGHT, PLASTIC, MO-252, SOT-886, SON-6, Gate Original PDF
    74AUP1G00GM,132 NXP Semiconductors Low-power 2-input NAND gate; Package: SOT886 (XSON6); Container: Tape reel smd Original PDF
    74AUP1G00GM-H NXP Semiconductors 74AUP1G00GM - Low-power 2-input NAND gate Original PDF
    74AUP1G00GM-H NXP Semiconductors Low-power 2-input NAND gate Original PDF
    74AUP1G00GN NXP Semiconductors Low-power 2-input NAND gate Original PDF
    ...

    74AUP Datasheets Context Search

    Catalog Datasheet MFG & Type Document Tags PDF

    74AUP1G80

    Abstract: 74AUP1G80GF 74AUP1G80GM 74AUP1G80GW MO-203
    Text: 74AUP1G80 Low-power D-type flip-flop; positive-edge trigger Rev. 01 — 20 October 2006 Product data sheet 1. General description The 74AUP1G80 is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families.


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    74AUP1G80 74AUP1G80 74AUP1G80GF 74AUP1G80GM 74AUP1G80GW MO-203 PDF

    74AUP1G19GM

    Abstract: 74AUP1G19GW JESD22-A114E
    Text: 74AUP1G19 Low-power 1-of-2 decoder/demultiplexer Rev. 01 — 13 August 2008 Product data sheet 1. General description The 74AUP1G19 provides a 1-of-2 decoder/demultiplexer with a common output enable. It buffers the data on input pin A and passes it either to output pin 1Y true or 2Y


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    74AUP1G19 74AUP1G19 74AUP1G19GM 74AUP1G19GW JESD22-A114E PDF

    74AUP2G125

    Abstract: 74AUP2G125DC 74AUP2G125GT JESD22-A114E JESD78
    Text: 74AUP2G125 Low-power dual buffer/line driver; 3-state Rev. 05 — 2 February 2009 Product data sheet 1. General description The 74AUP2G125 provides the dual non-inverting buffer/line driver with 3-state output. The 3-state output is controlled by the output enable input nOE . A HIGH level at pin nOE


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    74AUP2G125 74AUP2G125 74AUP2G125DC 74AUP2G125GT JESD22-A114E JESD78 PDF

    74AUP1G126

    Abstract: 74AUP1G32 JESD22-A114E 74AUP1T1326
    Text: 74AUP1T1326 Low-power dual supply buffer/line driver; 3-state Rev. 01 — 20 January 2009 Product data sheet 1. General description The 74AUP1T1326 is a high-performance, low-power, low-voltage, single-bit, dual supply buffer/line driver with output enable circuitry.


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    74AUP1T1326 74AUP1T1326 74AUP1G32 74AUP1G126. 74AUP1G126 JESD22-A114E PDF

    74AUP1G58

    Abstract: 74AUP1G58GF 74AUP1G58GM JESD22-A114E
    Text: 74AUP1G58 Low-power configurable multiple function gate Rev. 02 — 26 March 2009 Product data sheet 1. General description The 74AUP1G58 provides configurable multiple functions. The output state is determined by eight patterns of 3-bit input. The user can choose the logic functions AND, OR, NAND,


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    74AUP1G58 74AUP1G58 74AUP1G58GF 74AUP1G58GM JESD22-A114E PDF

    74AUP1G126

    Abstract: 74AUP1G126GF 74AUP1G126GM 74AUP1G126GW JESD22-A114-C MO-203
    Text: 74AUP1G126 Low-power buffer/line driver; 3-state Rev. 02 — 28 June 2006 Product data sheet 1. General description The 74AUP1G126 is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. Schmitt-trigger action at all


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    74AUP1G126 74AUP1G126 74AUP 74AUP1G126GF 74AUP1G126GM 74AUP1G126GW JESD22-A114-C MO-203 PDF

    74AUP2G240

    Abstract: 74AUP2G240DC 74AUP2G240GT JESD22-A114E JESD78
    Text: 74AUP2G240 Low-power dual inverting buffer/line driver; 3-state Rev. 03 — 7 April 2009 Product data sheet 1. General description The 74AUP2G240 provides the dual inverting buffer/line driver with 3-state output. The 3-state output is controlled by the output enable input nOE . A HIGH level at pin nOE


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    74AUP2G240 74AUP2G240 74AUP2G240DC 74AUP2G240GT JESD22-A114E JESD78 PDF

    74AUP1G00GW

    Abstract: 74AUP1G00 74AUP1G00GF 74AUP1G00GM
    Text: 74AUP1G00 Low-power 2-input NAND gate Rev. 3 — 7 October 2010 Product data sheet 1. General description The 74AUP1G00 provides the single 2-input NAND function. Schmitt-trigger action at all inputs makes the circuit tolerant to slower input rise and fall


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    74AUP1G00 74AUP1G00 74AUP1G00GW 74AUP1G00GF 74AUP1G00GM PDF

    74AUP2G157DC

    Abstract: 74AUP2G157GT
    Text: 74AUP2G157 Low-power 2-input multiplexer Rev. 4 — 30 July 2010 Product data sheet 1. General description The 74AUP2G157 is a single 2-input multiplexer which select data from two data inputs I0 and I1 under control of a common data select input (S). The state of the common data


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    74AUP2G157 74AUP2G157 74AUP2G157DC 74AUP2G157GT PDF

    74AUP1G34

    Abstract: 74AUP1G34GF 74AUP1G34GM 74AUP1G34GW
    Text: 74AUP1G34 Low-power buffer Rev. 4 — 14 July 2010 Product data sheet 1. General description The 74AUP1G34 provides a low-power, low-voltage single buffer. Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 0.8 V to 3.6 V.


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    74AUP1G34 74AUP1G34 74AUP1G34GF 74AUP1G34GM 74AUP1G34GW PDF

    74AUP1T34GF

    Abstract: 74AUP1T34GM MO-203
    Text: 74AUP1T34 Low-power dual supply translating buffer Rev. 2 — 19 August 2010 Product data sheet 1. General description The 74AUP1T34 provides a single buffer with two separate supply voltages. Input A is designed to track VCC A . Output Y is designed to track VCC(Y). Both, VCC(A) and VCC(Y)


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    74AUP1T34 74AUP1T34 74AUP1T34GF 74AUP1T34GM MO-203 PDF

    JESD22-A114E

    Abstract: No abstract text available
    Text: 74AUP1G09 Low-power 2-input AND gate with open-drain Rev. 2 — 9 July 2010 Product data sheet 1. General description The 74AUP1G09 provides the single 2-input AND gate with an open-drain output. The output of the device is an open-drain and can be connected to other open-drain outputs to


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    74AUP1G09 74AUP1G09 JESD22-A114E PDF

    74AUP1G0832

    Abstract: 74AUP1G0832GF 74AUP1G0832GM 74AUP1G0832GW
    Text: 74AUP1G0832 Low-power 3-input AND-OR gate Rev. 3 — 5 October 2010 Product data sheet 1. General description The 74AUP1G0832 provides the Boolean function: Y = A x B + C. The user can choose the logic functions OR, AND and AND-OR. All inputs can be connected to VCC or GND.


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    74AUP1G0832 74AUP1G0832 74AUP1G0832GF 74AUP1G0832GM 74AUP1G0832GW PDF

    74AUP2G14

    Abstract: 74AUP2G14GF 74AUP2G14GM 74AUP2G14GW
    Text: 74AUP2G14 Low-power dual Schmitt trigger inverter Rev. 3 — 22 July 2010 Product data sheet 1. General description The 74AUP2G14 provides two inverting buffers with Schmitt trigger action which accept standard input signals. They are capable of transforming slowly changing input signals


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    74AUP2G14 74AUP2G14 74AUP2G14GF 74AUP2G14GM 74AUP2G14GW PDF

    74AUP1G58L6X

    Abstract: 74AUP1G58 74AUP1G58FHX JESD22-A114 xnor
    Text: 74AUP1G58 TinyLogic Low Power Universal Configurable Two-Input Logic Gate Features Description ƒ ƒ 0.8V to 3.6V VCC Supply Operation ƒ High Speed tPD - 3.1ns: Typical at 3.3V ƒ ƒ Power-Off High-Impedance Inputs and Outputs The 74AUP1G58 is a universal configurable 2-input


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    74AUP1G58 74AUP1G58 74AUP1G58L6X 74AUP1G58FHX JESD22-A114 xnor PDF

    Untitled

    Abstract: No abstract text available
    Text: 74AUP1G126 SINGLE BUFFER GATE WITH 3-STATE OUTPUT Description Pin Assignments The Advanced Ultra Low Power AUP CMOS logic family is designed (Top View) for low power and extended battery life in portable applications. The 74AUP1G126 is a single non-inverting buffer/bus driver designed


    Original
    74AUP1G126 74AUP1G126 OT353 DS35158 PDF

    74AUP1G86SE

    Abstract: No abstract text available
    Text: 74AUP1G86 SINGLE 2 INPUT EXCLUSIVE-OR GATE Description Pin Assignments The Advanced Ultra Low Power AUP CMOS logic family is designed for low power and extended battery life in portable applications. The 74AUP1G86 is a single 2-input positive exclusive-OR gate with a


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    74AUP1G86 74AUP1G86 DS35156 74AUP1G86SE PDF

    74AUP1G07SE-7

    Abstract: 74AUP1G07
    Text: 74AUP1G07 SINGLE BUFFER/DRIVER WITH OPEN DRAIN OUTPUT Description Pin Assignments The Advanced Ultra Low Power AUP CMOS logic family is designed for low power and extended battery life in portable applications. The 74AUP1G07 is a single buffer gate with an open drain output


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    74AUP1G07 74AUP1G07 DS35149 74AUP1G07SE-7 PDF

    Untitled

    Abstract: No abstract text available
    Text: 74AUP1G38 Low-power 2-input NAND gate open drain Rev. 01 — 20 October 2006 Product data sheet 1. General description The 74AUP1G38 is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families.


    Original
    74AUP1G38 74AUP1G38 PDF

    74AUP1G58

    Abstract: 74AUP1G58GF 74AUP1G58GM
    Text: 74AUP1G58 Low-power configurable multiple function gate Rev. 4 — 11 October 2010 Product data sheet 1. General description The 74AUP1G58 provides configurable multiple functions. The output state is determined by eight patterns of 3-bit input. The user can choose the logic functions AND, OR, NAND,


    Original
    74AUP1G58 74AUP1G58 74AUP1G58GF 74AUP1G58GM PDF

    74AUP1G14

    Abstract: 74AUP1G14GF 74AUP1G14GM 74AUP1G14GW MO-203
    Text: 74AUP1G14 Low-power Schmitt trigger inverter Rev. 4 — 13 July 2010 Product data sheet 1. General description The 74AUP1G14 provides a single inverting Schmitt trigger which accepts standard input signals. It is capable of transforming slowly changing input signals into sharply defined,


    Original
    74AUP1G14 74AUP1G14 74AUP1G14GF 74AUP1G14GM 74AUP1G14GW MO-203 PDF

    74AUP2G241

    Abstract: 74AUP2G241DC 74AUP2G241GT
    Text: 74AUP2G241 Low-power dual buffer/line driver; 3-state Rev. 04 — 13 September 2010 Product data sheet 1. General description The 74AUP2G241 provides a dual non-inverting buffer/line driver with 3-state outputs. The 3-state outputs are controlled by the output enable inputs 1OE and 2OE. A HIGH


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    74AUP2G241 74AUP2G241 74AUP2G241DC 74AUP2G241GT PDF

    74AUP1G17

    Abstract: 74AUP1G17GF 74AUP1G17GM 74AUP1G17GW MO-203
    Text: 74AUP1G17 Low-power Schmitt trigger Rev. 4 — 15 July 2010 Product data sheet 1. General description The 74AUP1G17 provides the single Schmitt-trigger buffer. It is capable of transforming slowly changing input signals into sharply defined, jitter-free output signals.


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    74AUP1G17 74AUP1G17 74AUP1G17GF 74AUP1G17GM 74AUP1G17GW MO-203 PDF

    JESD22-C101E

    Abstract: No abstract text available
    Text: Demonstrate seven different logic functions NXP demo board for the configurable logic device 74AUP1T97 NXP demo board for the configurable logic device 74AUP1T97 Key features and benefits } Wide supply voltage range: 2.3 to 3.6 V } High noise immunity } Excellent ESD protection


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    74AUP1T97 JESD22-A114F JESD22-A115-A JESD22-C101E PDF