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    74AUP2G79GT Price and Stock

    Nexperia 74AUP2G79GT,115

    IC FF D-TYPE DUAL 1BIT 8XSON
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    NXP Semiconductors 74AUP2G79GT,115

    74AUP2G79GT - D Flip-Flop, AUP/ULP/V Series, 2-Func, Positive Edge Triggered, 1-Bit, True Output, CMOS, PDSO8
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    Rochester Electronics 74AUP2G79GT,115 131,543 1
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    NXP Semiconductors 74AUP2G79GT

    D FLIP-FLOP; Temperature Grade: AUTOMOTIVE; Terminal Form: NO LEAD; No. of Terminals: 8; Package Code: VSON; Package Shape: RECTANGULAR;
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    Vyrian 74AUP2G79GT 402
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    NXP Semiconductors 74AUP2G79GT-G

    D FLIP-FLOP; Temperature Grade: AUTOMOTIVE; Terminal Form: NO LEAD; No. of Terminals: 8; Package Code: VSON; Package Shape: RECTANGULAR;
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    Vyrian 74AUP2G79GT-G 372
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    74AUP2G79GT Datasheets (5)

    Part ECAD Model Manufacturer Description Curated Datasheet Type PDF
    74AUP2G79GT NXP Semiconductors Low-power dual D-type flip-flop, positive-edge trigger Original PDF
    74AUP2G79GT NXP Semiconductors Low-power dual D-type flip-flop; positive-edge trigger Original PDF
    74AUP2G79GT NXP Semiconductors 74AUP2G79 - IC AUP/ULP/V SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDSO8, 1 X 1.95 MM, 0.50 MM HEIGHT, PLASTIC, MO-252, SOT833-1, SON-8, FF/Latch Original PDF
    74AUP2G79GT,115 NXP Semiconductors Low-power dual D-type flip-flop; positive-edge trigger; Package: SOT833-1 (XSON8U); Container: Reel Pack, SMD, 7" Original PDF
    74AUP2G79GT,115 NXP Semiconductors 74AUP2G79 - IC AUP/ULP/V SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDSO8, 1 X 1.95 MM, 0.50 MM HEIGHT, PLASTIC, MO-252, SOT-833-1, SON-8, FF/Latch Original PDF

    74AUP2G79GT Datasheets Context Search

    Catalog Datasheet MFG & Type Document Tags PDF

    Dual D-type flip-flop positive-edge trigger

    Abstract: No abstract text available
    Text: 74AUP2G79 Low-power dual D-type flip-flop; positive-edge trigger Rev. 6 — 8 December 2011 Product data sheet 1. General description The 74AUP2G79 provides the dual positive-edge triggered D-type flip-flop. Information on the data input nD is transferred to the nQ output on the LOW-to-HIGH transition of the


    Original     		74AUP2G79 74AUP2G79 Dual D-type flip-flop positive-edge trigger PDF

    Dual D-type flip-flop positive-edge trigger

    Abstract: JESD22-A114E JESD78 74AUP2G79 74AUP2G79DC 74AUP2G79GT p79 marking
    Text: 74AUP2G79 Low-power dual D-type flip-flop; positive-edge trigger Rev. 04 — 30 June 2009 Product data sheet 1. General description The 74AUP2G79 provides the dual positive-edge triggered D-type flip-flop. Information on the data input nD is transferred to the nQ output on the LOW-to-HIGH transition of the


    Original     		74AUP2G79 74AUP2G79 Dual D-type flip-flop positive-edge trigger JESD22-A114E JESD78 74AUP2G79DC 74AUP2G79GT p79 marking PDF

    74AUP2G79

    Abstract: 74AUP2G79DC 74AUP2G79GM 74AUP2G79GT JESD22-A114E JESD78
    Text: 74AUP2G79 Low-power dual D-type flip-flop; positive-edge trigger Rev. 02 — 19 March 2008 Product data sheet 1. General description The 74AUP2G79 is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families.


    Original     		74AUP2G79 74AUP2G79 74AUP2G79DC 74AUP2G79GM 74AUP2G79GT JESD22-A114E JESD78 PDF

    Untitled

    Abstract: No abstract text available
    Text: 74AUP2G79 Low-power dual D-type flip-flop; positive-edge trigger Rev. 8 — 24 January 2013 Product data sheet 1. General description The 74AUP2G79 provides the dual positive-edge triggered D-type flip-flop. Information on the data input nD is transferred to the nQ output on the LOW-to-HIGH transition of the


    Original     		74AUP2G79 74AUP2G79 PDF

    74AUP2G79

    Abstract: 74AUP2G79DC 74AUP2G79GT JESD78
    Text: 74AUP2G79 Low-power dual D-type flip-flop; positive-edge trigger Rev. 5 — 30 September 2010 Product data sheet 1. General description The 74AUP2G79 provides the dual positive-edge triggered D-type flip-flop. Information on the data input nD is transferred to the nQ output on the LOW-to-HIGH transition of the


    Original     		74AUP2G79 74AUP2G79 74AUP2G79DC 74AUP2G79GT JESD78 PDF

    74AUP2G79

    Abstract: 74AUP2G79DC 74AUP2G79GM 74AUP2G79GT SN74AUC2G79 SN74AUC2G79DCTR
    Text: SLG74LB2G79 GreenLIBTM DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP General Description Features The GreenLIB provides a low-power, low-voltage dual • Pb-Free / RoHS Compliant positive-edge-triggered D-type flip-flop. When data at the • Halogen-Free data D input meets the setup time requirement, the data is


    Original     		SLG74LB2G79 LB2G79 000-0074LB2G79-11 74AUP2G79 74AUP2G79DC 74AUP2G79GM 74AUP2G79GT SN74AUC2G79 SN74AUC2G79DCTR PDF

    Untitled

    Abstract: No abstract text available
    Text: 74AUP2G79 Low-power dual D-type flip-flop; positive-edge trigger Rev. 01 — 6 October 2006 Product data sheet 1. General description The 74AUP2G79 is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families.


    Original     		74AUP2G79 74AUP2G79 PDF

    74AUP2G79

    Abstract: 74AUP2G79DC 74AUP2G79GT JESD22-A114E JESD78
    Text: 74AUP2G79 Low-power dual D-type flip-flop; positive-edge trigger Rev. 03 — 1 April 2009 Product data sheet 1. General description The 74AUP2G79 provides the dual positive-edge triggered D-type flip-flop. Information on the data input nD is transferred to the nQ output on the LOW-to-HIGH transition of the


    Original     		74AUP2G79 74AUP2G79 74AUP2G79DC 74AUP2G79GT JESD22-A114E JESD78 PDF

    Untitled

    Abstract: No abstract text available
    Text: 74AUP2G79 Low-power dual D-type flip-flop; positive-edge trigger Rev. 7 — 14 June 2012 Product data sheet 1. General description The 74AUP2G79 provides the dual positive-edge triggered D-type flip-flop. Information on the data input nD is transferred to the nQ output on the LOW-to-HIGH transition of the


    Original     		74AUP2G79 74AUP2G79 PDF