M74LS11P

Abstract: 20-PIN M74LS11
Contextual Info: MITSUBISHI LSTTLs 74LS11P TR IP LE 3 -IN P U T P O S ITIV E AND GATE DESCRIPTION The M 74LS11P is a s e m ico n d u c to r in teg rated c irc u it PIN CONFIGURATION TOP VIEW c o n ta in in g th re e tr ip le -in p u t positive A N D and negative O R gates.

74LS112A

Abstract: 74LS112 SN54/74LS112A truth table NOT gate 74 SN54LSXXXJ SN74LSXXXD SN74LSXXXN JD16
Contextual Info: SN54/74LS112A DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP The SN54 / 74LS112A dual JK flip-flop features individual J, K, clock, and asynchronous set and clear inputs to each flip-flop. When the clock goes HIGH, the inputs are enabled and data will be accepted. The logic level of the

ALU IC 74181

Abstract: 74181 ic pin diagram DS 7409 7480 full adder 1 bit 74LS86 full adder IC 74181 7411 3 INPUT AND gate TTL 74ls83 pin diagram of 7411 logic diagram of 7432
Contextual Info: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL-TTL D16 547408, 54H/74H08, 54S/74S08, 54LS/74LS08 54/7409, 54S/74S09, 54LS/74LS09 D18 54/7411, 54H/74H11, 54S/74S11, 54LS/74LS11, 54S/74S15, 54LS/74LS15 D17 9S41 Vcc Vcc 1^1FH [iä| [vii Eòi [T| r»1 füi Fai np f i ! Föi lyi rn

74S113D

Abstract: 74LS113D
Contextual Info: 113 C O N N E C T IO N DIAGRAM P IN O U T A 548/748113 * 54LS/74LS113 ö / / « 7 DUAL JK EDGE-TRIGGERED FLIP-FLOP D ESCRIPTION — T h e ’ 113 o ffe rs in d iv id u a l J, K, Set an d C lo c k inputs. W hen the c lo c k g o e s H IG H the in p u ts are e n a b le d and data m ay be entered.

Contextual Info: LS TTL DN74LS Series 74LS11 74LS11 D^74LS11 Triple 3-input P ositive AND Gates • Description P-1 D N 74L S 11 contains three 3-input positive isolation AND gate circuits. I Features • Low pow er consum ption P d = 13mW typical • High speed ( t pii = 9ns typical)

74LS113

Abstract: C0056
Contextual Info: 74LS113, S113 Signetics Flip-Flops Dual J-K Edge-Triggered Flip-Flop Product Specification Logic Products DESCRIPTION T h e '1 1 3 is a dual J-K negative edgetriggered flip-flop featuring individual J, K, S e t and Clock inputs. Th e asynchro­ nous S e t Sq input, w hen LOW , forces

74ls112 pin configuration

Abstract: 74ls112 function table 74LS112 74S112
Contextual Info: Signetics 74LS112, S112 Flip-Flops Dual J-K Edge-Triggered Flip-Flop Product Specification Logic Products DESCRIPTION The '112 is a dual J-K negative edgetriggered flip-flop featuring individual J, K, Clock, Set and Reset inputs. The Set So and Reset (R q) inputs, when LOW,

Contextual Info: SN 54LS112A , S N 54S 112, SN 74LS112A , S N 74S 112A DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP FLOPS W ITH PRESET AND CLEAR D 2 6 6 1 . APRIL 1 9 8 2 - REVISED M A R C H 1 9 8 8 Fully Buffered to Offer Maximum Isolation from External Disturbance r a a SN 54LS 112A , SN 54S 112 . . . J OR W PACKAGE

74ls112 pin diagram

Abstract: 74HC112
Contextual Info: GD54/74HC112, GD54/74HCT112 DUAL J-K FLIP-FLOPS WITH PRESET & CLEAR General Description These devices are identical in pinout to the 54/74LS112. They consist of two J-K flip-flops with individual J, K, CLOCK, PRESET, and CLEAR in­ puts. These flip-flops are edge sensitive to the clock

74LS11 pin configuration

Abstract: PIN CONFIGURATION 7411 74ls characteristics 7411 pin configuration N7411F N7411N N74H11F N74H11N N74LS11F N74LS11N
Contextual Info: 54/7411 54H/74H11 54S/74S11 54LS/74LS11 ORDERING CODE PIN CONFIGURATION See Section 9 for further Package and Ordering Information. C O M M E R C IA L RANGES ± 5%; Ta - 0°C to *70°C PACKAGES PIN CO N F. VCC = 5V P lastic DIP Fig. A Fig. A N 741 1 N N74S11N

74LS113

Abstract: 1N3064 1N916 74LS 74S113 N74LS113N N74S113N S113
Contextual Info: 74LS113, S 'it e Signetics Flip-Flops Dual J-K Edge-Triggered Flip-Flop Product Specification Logic Products DESCRIPTION T h e '1 1 3 is a dual J -K n e g a tive e dg e trig g e re d flip -flo p fe a tu rin g individ u a l J, K, S e t a n d C lo c k inp u ts. T h e a s y n c h ro ­

74ls112 pin diagram

Abstract: 74LS112 74ls112 pin configuration 74ls112 function table 74ls112 waveform 74LS 74S112 N74LS112D N74LS112N N74S112D
Contextual Info: 74LS112, S112 S ig n e tic s Flip-Flops Dual J-K Edge-Triggered Flip-Flop Product Specification Lo gic P roducts DESCRIPTION The '112 is a dual J-K negative edgetriggered flip-flop featuring individual J, K, Clock, Set and Reset inputs. The Set 3d and Reset (Rq) inputs, when LOW,

Contextual Info: MOTOROLA SN54/74LS114A DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP The S N 54/74LS 114A offers common clock and common d e a r inputs and individual J, K, and set inputs. These monolithic dual flip-flops are designed so that when the clock goes HIGH, the inputs are enabled and data will be

so 54 t

Abstract: 74ls 3-input and gate TTL IC 74 SN74LS 74LS11 Motorola 74LS TTL 74LS11 74ls11 ic for IC 74LS11 all gate ic data 74
Contextual Info: M MOTOROLA SN54/74LS11 TRIPLE 3-INPUT AND GATE TRIPLE 3-INPUT AND GATE v cc un r¡7j rrii rm nói m LOW POWER SCHOTTKY rn =§y n J SUFFIX C E R A M IC C A SE 632-08 14 GND 1 N SUFFIX PLA S TIC C A SE 646-06 D SUFFIX 14 1 SO IC C A S E 751A-02 5 ORDERING INFORMATION

Contextual Info: <8> MOTOROLA SN54/74LS114A D E S C R IPT IO N — The SN 54LS/74LS114A offers common clock and common clear inputs and individual J, K, and set inputs. These monolithic dual flip-flops are designed so that when the clock goes HIGH, the inputs are enabled and data w ill be accepted. The logic level

Contextual Info: MITSUBISHI LSTTLs M 74LS112AP DUAL J-K N EG A TIVE EDGE-TRIGGERED F L IP FLOPS W IT H SET AND RESET DESCRIPTION The M 7 4L S 11 2A P is a semiconductor integrated circuit containing 2 J-K negative edge-triggered flip -flo p circuits w ith discrete terminals fo r clock input T , J and K inputs

74LS114A

Abstract: truth table NOT gate 74 751A-02 SN54LSXXXJ SN74LSXXXD SN74LSXXXN 74LS114
Contextual Info: SN54/74LS114A DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP The SN54 / 74LS114A offers common clock and common clear inputs and individual J, K, and set inputs. These monolithic dual flip-flops are designed so that when the clock goes HIGH, the inputs are enabled and data will be

Contextual Info: GD54/74LS112 DUAL J-K NEGATIVE EDGE-TRIGGERED FLIP FLOPS WITH SET AND RESET Features Pin C o n fig u ra tio n • Negative edge-triggering • Diode clamped inputs • Independent input/output terminals for each flip-flop. • Direct set and reset inputs • Q and Q outputs

74LS114

Abstract: 74ls114d 74S114DC
Contextual Info: 114 C O N N E C T IO N D IA G R A M PINOUT A •01 ! .54S/74S114 54LS/74LS114 D I / ö H p 003 DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP c5{T 1 4 ] Vcc k , T (With Common Clocks and Clears K, C P J i CO S pi Qi Qi Ji[ T n ] cp m D E S C R IP T IO N — The '114 features individual J, K and set inputs and com­

74LS11

Abstract: 74S11 54ls11
Contextual Info: S N 54LS11, SN54S11, SN 74LS11, SN74S11 TRIPLE 3-INPUT POSITIVE AND GATES A PRIL 19 85 —R EV ISED MARCH 1988 S N 5 4 L S 1 1 . S N 7 4 S 1 1 . . . J OR W P A C K A G E SN 74LS11. SN 74S11 c 1 U 14 : 13 : 2 12 q 3 11 : c4 10 c 5 9 : c6 1A c IB Dependable Texas Instruments Quality and

74 LS 193 Logic DIAGRAM

Abstract: truth table NOT gate 74 751A-02 SN54LSXXXJ SN74LSXXXD SN74LSXXXN
Contextual Info: SN54/74LS114A DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP The SN54/ 74LS114A offers common clock and common clear inputs and individual J, K, and set inputs. These monolithic dual flip-flops are designed so that when the clock goes HIGH, the inputs are enabled and data will be

Contextual Info: 112 CONNECTION DIAGRAM P IN O U T A 54S/74S112 t1" 00 \/&4LS/74LS112 b DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP DESCRIPTION — The '112 features individual J, K, C lo ck and asynchronous Set and C lear inputs to each flip-flop. When the clo ck goes HIGH, the inputs

74LS113

Contextual Info: 74LS113, S113 Signetics Flip-Flops Dual J-K Edge-Triggered Flip-Flop Product Specification Logic Products DESCRIPTION The '113 is a dual J-K negative edgetriggered flip-flop featuring individual J, K, Set and Clock inputs. The asynchro­ nous Set S d input, w hen LOW, forces

Contextual Info: M O T O R O LA . SN54/74LS11 r r r r r m r TRIPLE 3-INPUT A N D G ATE "L 3 U LiJ U LiJ H I LlJ LO W POWER SCHO TTKY J Suffix — Case 632-08 Ceramic N Suffix — Case 646-06 (Plastic) GUARANTEED OPERATING RANGES SYM B O L MIN TYP MAX UNIT Vcc Supply Voltage