Untitled
Abstract: No abstract text available
Text: 7601SG-Infrared Emitting Diodes IRED Description H E 7601S G is a 0.77 G aA lA s infrared e m it ting d io d e with double heterojunction structure. H igh brightness o u tp u t, high pow er o u tp u t and high speed resp onse can be obtained. It is suitable as a light source in optical control
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HE7601SG---Infrared
7601S
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Untitled
Abstract: No abstract text available
Text: XRT75L04 xr FOUR CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR JANUARY 2006 GENERAL DESCRIPTION The XRT75L04 is a four-channel fully integrated Line Interface Unit LIU with Jitter Attenuator for E3/DS3/ STS-1 applications. It incorporates four independent
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XRT75L04
XRT75L04
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Untitled
Abstract: No abstract text available
Text: XRT73LC03A 3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT REV. 1.0.4 GENERAL DESCRIPTION The XRT73LC03A, 3-Channel, DS3/E3/STS-1 Line Interface Unit is a low power CMOS version of the XRT73L03A and consists of three independent line transmitters and receivers integrated on a single chip
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XRT73LC03A
XRT73LC03A,
XRT73L03A
XRT73LC03A
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rneg2
Abstract: GR-253-CORE GR-499-CORE XRT71D03 XRT72L56 XRT73L03A XRT73L03B XRT73L03BIV XRT74L73 Theta-JC sol
Text: XRT73L03B 3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT OCTOBER 2003 REV. 1.0.1 GENERAL DESCRIPTION The XRT73L03B, 3-Channel, DS3/E3/STS-1 Line Interface Unit is a low power CMOS version of the XRT73L03A and consists of three independent line transmitters and receivers integrated on a single chip
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XRT73L03B
XRT73L03B,
XRT73L03A
XRT73L03A
XRT73L03B
rneg2
GR-253-CORE
GR-499-CORE
XRT71D03
XRT72L56
XRT73L03BIV
XRT74L73
Theta-JC sol
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HDB3 CODING DECODING FPGA
Abstract: chn 834 chn 832 R13C7 CHN 833 GR-253 GR-253-CORE GR-499-CORE XRT75R06D FPGA AMI coding decoding
Text: áç XRT75R06D SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER DECEMBER 2004 REV. 1.0.0 GENERAL DESCRIPTION The XRT75R06D is a six channel fully integrated Line Interface Unit LIU featuring EXAR’s R3 Technology (Reconfigurable, Relayless, Redundancy) for E3/
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XRT75R06D
XRT75R06D
HDB3 CODING DECODING FPGA
chn 834
chn 832
R13C7
CHN 833
GR-253
GR-253-CORE
GR-499-CORE
FPGA AMI coding decoding
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GR-253-CORE
Abstract: GR-499-CORE PE-65966 PE-65967 PE-68629 XRT73L02 XRT73L02A 362T 22an
Text: áç XRT73L02A PRELIMINARY 2 CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT NOVEMBER 2001 REV. 2.0.0 GENERAL DESCRIPTION FEATURES The XRT73L02A Dual Channel E3/DS3/STS-1 Transceiver is an improved version of the XRT73L02 and consists of two fully integrated transmitter and receiver line transceivers designed for E3, DS3 or SONET
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Original
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XRT73L02A
XRT73L02A
XRT73L02
XRT73L02
GR-253-CORE
GR-499-CORE
PE-65966
PE-65967
PE-68629
362T
22an
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JA02
Abstract: ana 608 GR-253 GR-253-CORE GR-499-CORE XRT75L04D XRT75L04DIV chn 347
Text: áç XRT75L04D FOUR CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER NOVEMBER 2003 GENERAL DESCRIPTION The XRT75L04D is a four-channel fully integrated Line Interface Unit LIU with Sonet Desynchronizer for E3/DS3/STS-1 applications. It incorporates four
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Original
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XRT75L04D
XRT75L04D
JA02
ana 608
GR-253
GR-253-CORE
GR-499-CORE
XRT75L04DIV
chn 347
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0X00
Abstract: GR-253-CORE GR-499-CORE XRT73L00 XRT73L00IV
Text: áç XRT73L00 E3/DS3/STS-1 LINE INTERFACE UNIT JULY 2001 REV. 1.2.0 FEATURES • Meets E3/DS3/STS-1 Jitter Tolerance Requirements GENERAL DESCRIPTION The XRT73L00 DS3/E3/STS-1 Line Interface Unit is designed to be used in DS3, E3 or SONET STS-1 applications and consists of a line transmitter and receiver integrated on a single chip.
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XRT73L00
XRT73L00
0X00
GR-253-CORE
GR-499-CORE
XRT73L00IV
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CHN 523
Abstract: CHN 522
Text: XRT75L06D SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER MARCH 2004 REV. 1.0.3 GENERAL DESCRIPTION attenuators can be used for clock smoothing in SONET STS-1 to DS-3 de-mapping. The XRT75L06D is a six channel fully integrated Line Interface Unit LIU for E3/DS3/STS-1 applications.
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XRT75L06D
XRT75L06D
CHN 523
CHN 522
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chn 752
Abstract: HDB3 CODING DECODING FPGA chn 501 chn 732
Text: XRT75L06D SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER OCTOBER 2003 REV. 1.0.2 GENERAL DESCRIPTION attenuators can be used for clock smoothing in SONET STS-1 to DS-3 de-mapping. The XRT75L06D is a six channel fully integrated Line
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XRT75L06D
XRT75L06D
chn 752
HDB3 CODING DECODING FPGA
chn 501
chn 732
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Untitled
Abstract: No abstract text available
Text: XRT73L03B 3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT JULY 2003 REV. 1.0.0 GENERAL DESCRIPTION The XRT73L03B, 3-Channel, DS3/E3/STS-1 Line Interface Unit is a low power CMOS version of the XRT73L03A and consists of three independent line transmitters and receivers integrated on a single chip
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XRT73L03B
XRT73L03B,
XRT73L03A
XRT73L03B
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Untitled
Abstract: No abstract text available
Text: xr XRT75L02 TWO CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER DECEMBER 2005 GENERAL DESCRIPTION REV. 1.0.3 • Provides low jitter clock outputs for either DS3,E3 or STS-1 rates. The XRT75L02 is a two-channel fully integrated Line Interface Unit LIU with Jitter Attenuator for E3/DS3/
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XRT75L02
XRT75L02
XRT75L02IV-F
TQFP100
31-Jul-09
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Untitled
Abstract: No abstract text available
Text: xr XRT75L02 TWO CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER DECEMBER 2005 GENERAL DESCRIPTION REV. 1.0.3 • Provides low jitter clock outputs for either DS3,E3 or STS-1 rates. The XRT75L02 is a two-channel fully integrated Line Interface Unit LIU with Jitter Attenuator for E3/DS3/
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XRT75L02
XRT75L02
XRT75L02D
XRT75L02DIV-F
TQFP100
31-Jul-09
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XRT73L00A
Abstract: No abstract text available
Text: XRT73LC00A E3/DS3/STS-1 LINE INTERFACE UNIT AUGUST 2008 REV. 1.0.1 GENERAL DESCRIPTION FEATURES The XRT73LC00A DS3/E3/STS-1 Line Interface Unit is a low power CMOS version of the XRT73L00A and consists of a line transmitter and receiver integrated on a single chip and is designed for DS3, E3 or
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XRT73LC00A
XRT73LC00A
XRT73L00A
15-Nov-2010
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0X00
Abstract: GR-253-CORE GR-499-CORE XRT73L00 XRT73L00A XRT73L00AIV
Text: áç XRT73L00A E3/DS3/STS-1 LINE INTERFACE UNIT SEPTEMBER 2001 REV. 1.3.0 FEATURES • Incorporates an improved Timing Recovery circuit and is pin and functional compatible to XRT73L00 GENERAL DESCRIPTION The XRT73L00A DS3/E3/STS-1 Line Interface Unit is an improved version of the XRT73L00 and consists of
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XRT73L00A
XRT73L00
XRT73L00A
XRT73L00
0X00
GR-253-CORE
GR-499-CORE
XRT73L00AIV
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GR-499-CORE
Abstract: XRT71D04 XRT72L58 XRT73L04A XRT73LC04A XRT73LC04AIV XRT74L74
Text: áç XRT73LC04A PRELIMINARY 4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT SEPTEMBER 2002 REV. P1.0.1 GENERAL DESCRIPTION The XRT73LC04A, 4-Channel, DS3/E3/STS-1 Line Interface Unit is a low power CMOS version of the XRT73L04A and consists of four independent line
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XRT73LC04A
XRT73LC04A,
XRT73L04A
XRT73L04A
XRT73LC04A
GR-499-CORE
XRT71D04
XRT72L58
XRT73LC04AIV
XRT74L74
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GR-253-CORE
Abstract: GR-499-CORE XRT71D04 XRT72L58 XRT73L04A XRT73LC04A XRT73LC04AIV XRT74L74
Text: XRT73LC04A 4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT SEPTEMBER 2008 REV. 1.0.2 GENERAL DESCRIPTION The XRT73LC04A, 4-Channel, DS3/E3/STS-1 Line Interface Unit is a low power CMOS version of the XRT73L04A and consists of four independent line transmitters and receivers integrated on a single chip
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XRT73LC04A
XRT73LC04A,
XRT73L04A
XRT73L04A
XRT73LC04A
GR-253-CORE
GR-499-CORE
XRT71D04
XRT72L58
XRT73LC04AIV
XRT74L74
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pe-68629
Abstract: GR-253 GR-253-CORE GR-499-CORE XRT75L04 XRT75L04IV 75L04
Text: XRT75L04 FOUR CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER JULY 2006 GENERAL DESCRIPTION The XRT75L04 is a four-channel fully integrated Line Interface Unit LIU with Jitter Attenuator for E3/DS3/ STS-1 applications. It incorporates four independent
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Original
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XRT75L04
XRT75L04
pe-68629
GR-253
GR-253-CORE
GR-499-CORE
XRT75L04IV
75L04
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chn 751
Abstract: GR-253 GR-253-CORE GR-499-CORE XRT75R06D XRT75R06DIB chn 622 st WG 253 chn 834 HDB3 CODING DECODING FPGA
Text: xr XRT75R06D PRELIMINARY SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER JULY 2004 REV. 1.0.0 GENERAL DESCRIPTION The XRT75R06D is a six channel fully integrated Line Interface Unit LIU featuring EXAR’s R3 Technology (Reconfigurable, Relayless, Redundancy) for E3/
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XRT75R06D
XRT75R06D
chn 751
GR-253
GR-253-CORE
GR-499-CORE
XRT75R06DIB
chn 622 st
WG 253
chn 834
HDB3 CODING DECODING FPGA
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GR-253
Abstract: GR-253-CORE GR-499-CORE XRT75L02D XRT75L03 D6/chn 609
Text: áç XRT75L02D TWO CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER NOVEMBER 2003 GENERAL DESCRIPTION REV. 1.0.1 • Provides low jitter clock outputs for either DS3,E3 or STS-1 rates. The XRT75L02D is a two-channel fully integrated Line Interface Unit LIU with Sonet Desynchronizer
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Original
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XRT75L02D
XRT75L02D
GR-253
GR-253-CORE
GR-499-CORE
XRT75L03
D6/chn 609
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GR-253-CORE
Abstract: GR-499-CORE XRT71D04 XRT72L58 XRT73L04A XRT73LC04A XRT73LC04AIV XRT74L74
Text: XRT73LC04A 4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT OCTOBER 2003 REV. 1.0.1 GENERAL DESCRIPTION The XRT73LC04A, 4-Channel, DS3/E3/STS-1 Line Interface Unit is a low power CMOS version of the XRT73L04A and consists of four independent line transmitters and receivers integrated on a single chip
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Original
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XRT73LC04A
XRT73LC04A,
XRT73L04A
XRT73L04A
XRT73LC04A
GR-253-CORE
GR-499-CORE
XRT71D04
XRT72L58
XRT73LC04AIV
XRT74L74
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T73LC00
Abstract: 0X00 GR-253-CORE GR-499-CORE XRT73L00A XRT73LC00 XRT73LC00IV M3015
Text: áç XRT73LC00 PRELIMINARY E3/DS3/STS-1 LINE INTERFACE UNIT AUGUST 2002 REV. P1.0.1 FEATURES • Incorporates an improved Timing Recovery circuit and is pin and functional compatible to XRT73L00A GENERAL DESCRIPTION The XRT73LC00 DS3/E3/STS-1 Line Interface Unit is
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XRT73LC00
XRT73L00A
XRT73LC00
XRT73L00A
T73LC00
0X00
GR-253-CORE
GR-499-CORE
XRT73LC00IV
M3015
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Untitled
Abstract: No abstract text available
Text: XRT75L06 SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR OCTOBER 2003 REV. 1.0.2 GENERAL DESCRIPTION The XRT75L06 is a six Interface Unit LIU for The LIU incorporates Transmitters and Jitter Lead BGA package. attenuator performance meets the ETSI TBR-24 and
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XRT75L06
XRT75L06
TBR-24
GR-499
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hw rev.2.02
Abstract: No abstract text available
Text: áç XRT73L02A 2 CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT JANUARY 2003 REV. 2.0.2 GENERAL DESCRIPTION FEATURES The XRT73L02A Dual Channel E3/DS3/STS-1 Transceiver is an improved version of the XRT73L02 and consists of two fully integrated transmitter and receiver line transceivers designed for E3, DS3 or SONET
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Original
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XRT73L02A
XRT73L02A
XRT73L02
hw rev.2.02
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