7C381 Search Results

CY7C381P-2JC

Abstract: CY7C381P-2JI vial
Contextual Info: 7C381A: Monday, September 20, 1993 Revision: October 9, 1995 7C381P CY7C382P UltraLogict Very High Speed 1K Gate CMOS FPGA Features D Very high speed D D D D D D Ċ Loadable counter frequencies greater than 150 MHz Ċ ChipĆtoĆchip operating frequencies

Contextual Info: 7c3816: October 9, 1995 Revision: October 25, 1995 Ultra38016 ADVANCED INFORMATION UltraLogict Very High Speed 16K Gate CMOS FPGA Features D Very high speed D D D D D D Ċ Loadable counter frequencies greater than 185 MHz Ċ ChipĆtoĆchip operating frequencies

Contextual Info: 7c3812: October 9, 1995 Revision: October 25, 1995 Ultra38012 ADVANCED INFORMATION UltraLogict Very High Speed 12K Gate CMOS FPGA D Robust routing resources Features D Very high speed D D D D D D Ċ Loadable counter frequencies greater than 185 MHz Ċ ChipĆtoĆchip operating frequencies

CY7C381P

Abstract: CY7C381P-0JC CY7C381P-XJC CY7C381P-XJI CY7C382P CY7C383A CY7C385P 100-Pin CPGA Package Pin-Out Diagram
Contextual Info: 7C381P CY7C382P CYPRESS Features • Very high speed — Loadable counter frequencies greater than 150 MHz — Chip-to-chip operating frequencies up to 110 MHz — Input + logic cell + output delays under 6 ns • Unparalleled FPGA performance for counters, data path, state machines,

frws 5-4

Abstract: CY7C381-0JI C3816 G68 Package vhdl code for lte channel coding CY7C381 CY7C382 7c381 C381-9 C3812
Contextual Info: ¡iiö i id in tJ . iv iu iiu c iy , M u y u t ji i / , Revision: Wednesday, March 16,1994 ¥ 7C381 CY7C382 cypress Features • Very high speed — Loadable counter frequencies greater than 100 MHz — Chip-to-chip operating frequencies up to 85 MHz — Input + logic cell + output delays

Contextual Info: tvjooim. iviunuay, oepiariiuei ¿u, i»»o Revision: Tuesday, May 10,1994 r# CYPRESS Features • Very high speed — Loadable counter frequencies greater than 150 MHz — Chip-to-chip operating frequencies up to 120 MHz — Input + logic cell + output delays

Contextual Info: Revision: Thursday, September 24,1992 MUR 23 1993 PRELIMINARY CYPRESS s7-W '" SEMICONDUCTOR Features • Very high speed — Loadable counter frequencies greater than 100 MHz — Chip-to-chip operating frequencies up to 85 MHz — Input + logic cell + output delays

Contextual Info: Revision: Monday, December 14,1992 a* 7C381 CY7C382 PRELIMINARY H v p p rc c — Very High Speed IK 3K Gate CMOS FPGA SEMICONDUCTOR Features • Very high speed — Loadable counter frequencies greater than 100 MHz — Chip-to-chip operating frequencies

81c78

Abstract: 7C291 5962-8515505RX 27PC256-12 PAL164A 8464C 5C6408 72018 39C10B MACH110 cross reference
Contextual Info: Product Line Cross Reference CYPRESS 2147-35C 2147-45C 2147-45C 2147-45M+ 2147-55C 2147-55M 2148-35C 2148-35C 2148-35M 2148-45C 2148-45C 2148-45M 2148-45M+ 2148-55C 2148-55C 2148-55M 2149-35C 2149-35C 2149-35M 2149-45C 2149-45M 2149-45M 2149-55C 2149-55C 2149-55M

7C385

Abstract: CY7C385 CY7C380
Contextual Info: CY7C380 Family Quick Power Calculator This brief is intended to provide a rapid method of calculating the approximate power consumed by a CY7C380 family device. Because the intent is a firstĆestimate calculation, some details are neĆ glected. The quiescent power of about 20 mW is not

CY7C381A

Contextual Info: 7C381A CY7C382A r# CYPRESS Very High Speed IK 3K Gate CMOS FPGA — Waveform simulation with back annotated net delays — PC and workstation platforms Robust routing resources — Fully automatic place and route of designs using up to 100 percent of logic resources

CY7C381A

Abstract: CY7C381A-OJI CY7C382A
Contextual Info: 7C381A CY7C382A # CYPRESS Very High Speed IK 3K Gate CMOS FPGA — Waveform simulation with back annotated net delays — PC and workstation platforms Robust routing resources — Fully automatic place and route of designs using up to 100 percent of logic resources

programmer manual EPLD cypress

Abstract: pASIC380 programming manual EPLD CY7C383A GAL programmer schematic
Contextual Info: filename: Tuesday, August 11, 1992 Revision: October 9, 1995 pASIC380 Family UltraLogict Very High Speed CMOS FPGAs D Robust routing resources Features D Very high speed D D D D D D D Ċ Loadable counter frequencies greater than 150 MHz Ċ ChipĆtoĆchip operating frequencies

pasic380

Abstract: CY7C382A-2JI CY7C381A CY7C381A-2JI
Contextual Info: 7C381A CY7C382A # CYPRESS Very High Speed IK 3K Gate CMOS FPGA — Waveform simulation with back annotated net delays — PC and workstation platforms Robust routing resources — Fully automatic place and route of designs using up to 100 percent of logic resources

C3807 equivalent

Contextual Info: PRELIMINARY r-’vpprcq SEMICONDUCTOR Very High Speed CMOS FPGAs • Input hysteresis provides high noise immunity • Thorough testability — Built-in scan path permits 100 per­ cent factory testing of logic and I/O cells — Automatic Test Vector Generation

programmer manual EPLD cypress

Contextual Info: l l lt fM d l l l t? . I U t? 5 U d y , M U y U 5 > l I I , ItKfcS Revision: Tuesday, June 28,1994 pASIC380 Family F/ CYPRESS Features • Very high speed — Loadable counter frequencies greater than 100 MHz — Chip-to-chip operating frequencies up to 85 MHz

Contextual Info: PRELIMINARY CYPRESS SEMICONDUCTOR Features • Very high speed — Loadable counter frequencies greater than 100 MHz — Chip-to-chip operating frequencies up to 85 MHz — Input + logic cell + output delays under 9 ns Very High Speed IK 3K Gate CMOS FPGA

Contextual Info: 7C381P CY7C382P CYPRESS Features • Very high speed — Loadable counter frequencies greater than 150 MHz — Chip-to-chip operating frequencies up to 110 MHz — Input + logic cell + output delays under 6 ns • Unparalleled FPGA performance for counters, data path, state machines,

Contextual Info: > CYPRESS Features • Full 33V operation • Very high speed — Loadable counter frequencies greater than 100 MHz — Chip-8-chip operating frequencies up to 85 MHz — Input + logic cell + output delays under 7 ns • Unparalleled FPGA performance for counters, data path, state machines,