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    dhvqfn14

    Abstract: 74AHCT08D NXP 74AHC08 74AHC08BQ 74AHC08D 74AHC08PW 74AHCT08 74AHCT08D 74AHCT08PW JESD22-A114E
    Text: 74AHC08; 74AHCT08 NXP Semiconductors Quad 2-input AND gate 4. Functional diagram 1 & 3 & 6 2 1 1A 2 1B 4 2A 5 2B 9 3A 10 3B 12 4A 13 4B 1Y 3 4 2Y 6 5 3Y 8 9 A Y & 8 B 10 4Y mna221 11 12 mna222 & 11 13 mna223 Fig 1. Logic symbol Fig 2. IEC logic symbol Fig 3. Logic diagram one gate


    Original     		PDF 74AHC08; 74AHCT08 74AHCT08 74AHC08 JESD22-A114E JESD22-A115-A dhvqfn14 74AHCT08D NXP 74AHC08BQ 74AHC08D 74AHC08PW 74AHCT08D 74AHCT08PW

    Untitled

    Abstract: No abstract text available
    Text: 74LVC1G08 Single 2-input AND gate Rev. 9 — 9 December 2011 Product Specification 1. General description The 74LVC1G08 provides one 2-input AND function. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V applications.


    Original     		PDF 74LVC1G08 74LVC1G08 771-LVC1G08GWDG125 74LVC1G08GW/DG

    74AHC2G08

    Abstract: 74AHC2G08DC 74AHC2G08DP 74AHCT2G08 74AHCT2G08DC 74AHCT2G08DP JESD22-A114E
    Text: 74AHC2G08; 74AHCT2G08 Dual 2-input AND gate Rev. 03 — 12 January 2009 Product data sheet 1. General description The 74AHC2G08; 74AHCT2G08 is a high-speed Si-gate CMOS device. The 74AHC2G08; 74AHCT2G08 provides two 2-input AND gates. 2. Features • Symmetrical output impedance


    Original     		PDF 74AHC2G08; 74AHCT2G08 74AHCT2G08 JESD22-A114E JESD22-A115-A JESD22-C101C 74AHC2G08DP 74AHC2G08 74AHC2G08DC 74AHC2G08DP 74AHCT2G08DC 74AHCT2G08DP

    21A1

    Abstract: 74LV125DB 74HC125 74HCT125 74LV125 74LV125D 74LV125N 74LV125PW JESD22-A114E
    Text: 74LV125 Quad buffer/line driver; 3-state Rev. 03 — 7 April 2009 Product data sheet 1. General description The 74LV125 is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HC125 and 74HCT125. The 74LV125 provides four non-inverting buffer/line drivers with 3-state outputs. The


    Original     		PDF 74LV125 74LV125 74HC125 74HCT125. 21A1 74LV125DB 74HCT125 74LV125D 74LV125N 74LV125PW JESD22-A114E

    AHCT32

    Abstract: 74AHC32 74AHC32BQ 74AHC32D 74AHC32PW 74AHCT32 TSSOP14
    Text: 74AHC32; 74AHCT32 Quad 2-input OR gate Rev. 04 — 22 May 2008 Product data sheet 1. General description The 74AHC32; 74AHCT32 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL LSTTL . It is specified in compliance with JEDEC standard


    Original     		PDF 74AHC32; 74AHCT32 74AHCT32 74AHC32: 74AHCT32: EIA/JESD22-A114E EIA/JESD22-A115-A AHCT32 74AHC32 74AHC32BQ 74AHC32D 74AHC32PW TSSOP14

    74AUP2G125

    Abstract: 74AUP2G125DC 74AUP2G125GT JESD22-A114E JESD78
    Text: 74AUP2G125 Low-power dual buffer/line driver; 3-state Rev. 05 — 2 February 2009 Product data sheet 1. General description The 74AUP2G125 provides the dual non-inverting buffer/line driver with 3-state output. The 3-state output is controlled by the output enable input nOE . A HIGH level at pin nOE


    Original     		PDF 74AUP2G125 74AUP2G125 74AUP2G125DC 74AUP2G125GT JESD22-A114E JESD78

    74LVC2G86

    Abstract: 74LVC2G86DC 74LVC2G86DP 74LVC2G86GM 74LVC2G86GT
    Text: 74LVC2G86 Dual 2-input EXCLUSIVE-OR gate Rev. 8 — 19 October 2010 Product data sheet 1. General description The 74LVC2G86 provides a dual 2-input EXCLUSIVE-OR gate. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these


    Original     		PDF 74LVC2G86 74LVC2G86 74LVC2G86DC 74LVC2G86DP 74LVC2G86GM 74LVC2G86GT

    74LVC2G32

    Abstract: 74LVC2G32DC 74LVC2G32DP 74LVC2G32GM 74LVC2G32GT XSON8 SOT1116
    Text: 74LVC2G32 Dual 2-input OR gate Rev. 8 — 10 November 2010 Product data sheet 1. General description The 74LVC2G32 provides a 2-input OR gate function. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in a mixed 3.3 V and 5 V environment.


    Original     		PDF 74LVC2G32 74LVC2G32 74LVC2G32DC 74LVC2G32DP 74LVC2G32GM 74LVC2G32GT XSON8 SOT1116

    74LVC2G32

    Abstract: 74LVC2G32DC 74LVC2G32DP 74LVC2G32GM 74LVC2G32GT MO-187 VSSOP8
    Text: 74LVC2G32 Dual 2-input OR gate Rev. 06 — 27 February 2008 Product data sheet 1. General description The 74LVC2G32 provides a 2-input OR gate function. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in a mixed 3.3 V and 5 V environment.


    Original     		PDF 74LVC2G32 74LVC2G32 74LVC2G32DC 74LVC2G32DP 74LVC2G32GM 74LVC2G32GT MO-187 VSSOP8

    74ALVC125

    Abstract: 74ALVC125D 74ALVC125PW TSSOP14
    Text: INTEGRATED CIRCUITS DATA SHEET 74ALVC125 Quad buffer/line driver; 3-state Product specification 2002 Nov 18 Philips Semiconductors Product specification Quad buffer/line driver; 3-state 74ALVC125 FEATURES DESCRIPTION • Wide supply voltage range from 1.65 to 3.6 V


    Original     		PDF 74ALVC125 74ALVC125 JESD8B/JESD36 SCA74 613508/01/pp16 74ALVC125D 74ALVC125PW TSSOP14

    Untitled

    Abstract: No abstract text available
    Text: 74AHC2G32; 74AHCT2G32 Dual 2-input OR gate Rev. 01 — 23 February 2004 Product data sheet 1. General description The 74AHC2G/AHCT2G32 is a high-speed Si-gate CMOS device. This device provides two 2-input OR gates. 2. Features • Symmetrical output impedance


    Original     		PDF 74AHC2G32; 74AHCT2G32 74AHC2G/AHCT2G32 EIA/JESD22-A114-A EIA/JESD22-A115-A EIA/JESD22-C101 OT505-2 OT765-1

    Untitled

    Abstract: No abstract text available
    Text: 74AUP2G08 Low-power dual 2-input AND gate Rev. 5 — 1 December 2011 Product data sheet 1. General description The 74AUP2G08 provides the dual 2-input AND function. Schmitt-trigger action at all inputs makes the circuit tolerant to slower input rise and fall


    Original     		PDF 74AUP2G08 74AUP2G08

    Untitled

    Abstract: No abstract text available
    Text: 74AUP1G08 Low-power 2-input AND gate Rev. 4 — 15 November 2011 Product data sheet 1. General description The 74AUP1G08 provides the single 2-input AND function. Schmitt-trigger action at all inputs makes the circuit tolerant to slower input rise and fall


    Original     		PDF 74AUP1G08 74AUP1G08

    Untitled

    Abstract: No abstract text available
    Text: 74AUP1G08 Low-power 2-input AND gate Rev. 5 — 12 April 2012 Product data sheet 1. General description The 74AUP1G08 provides the single 2-input AND function. Schmitt-trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 0.8 V to 3.6 V.


    Original     		PDF 74AUP1G08 74AUP1G08

    Untitled

    Abstract: No abstract text available
    Text: 74LV86 Quad 2-input exclusive-OR gate Rev. 03 — 27 November 2007 Product data sheet 1. General description The 74LV86 is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HC86 and 74HCT86. The 74LV86 provides a quad 2-input exclusive-OR function.


    Original     		PDF 74LV86 74LV86 74HC86 74HCT86. JESD22-A114E JESD22-A115-A

    74LVC125A

    Abstract: 74LVC125AD 74LVC125ADB 74LVC125APW
    Text: INTEGRATED CIRCUITS DATA SHEET 74LVC125A Quad buffer/line driver with 5 Volt tolerant input/outputs; 3-state Product specification Supersedes data of 1998 Apr 28 2002 Mar 08 Philips Semiconductors Product specification Quad buffer/line driver with 5 Volt tolerant input/outputs;


    Original     		PDF 74LVC125A 74LVC125A SCA74 613508/03/pp16 74LVC125AD 74LVC125ADB 74LVC125APW

    74HC08

    Abstract: 74HCT08 74HC08D 74HC08DB 74HC08N 74HCT08D 74HCT08N 74HC08PW
    Text: Philips Semiconductors Product specification Quad 2-input AND gate 74HC08; 74HCT08 FEATURES DESCRIPTION • Complies with JEDEC standard no. 8-1A The 74HC/HCT08 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL LSTTL . They are specified in compliance with JEDEC


    Original     		PDF 74HC08; 74HCT08 74HC/HCT08 EIA/JESD22-A114-A EIA/JESD22-A115-A 74HC08 OT402-1 MO-153 74HC08 74HCT08 74HC08D 74HC08DB 74HC08N 74HCT08D 74HCT08N 74HC08PW

    MNA220

    Abstract: 74ALVC08 74ALVC08BQ 74ALVC08D 74ALVC08PW DHVQFN14 TSSOP14 JESD87
    Text: Philips Semiconductors Product specification Quad 2-input AND gate 74ALVC08 FEATURES DESCRIPTION • Wide supply voltage range from 1.65 to 3.6 V The 74ALVC08 is a high-performance, low-power, low-voltage, Si-gate CMOS device and superior to most advanced CMOS compatible TTL families.


    Original     		PDF 74ALVC08 74ALVC08 JESD8B/JESD36 OT108-1 076E06 MS-012 MNA220 74ALVC08BQ 74ALVC08D 74ALVC08PW DHVQFN14 TSSOP14 JESD87

    11851

    Abstract: 74LVC2G86 74LVC2G86DP
    Text: INTEGRATED CIRCUITS DATA SHEET 74LVC2G86 Dual 2-input exclusive-OR gate Product specification 2003 Aug 25 Philips Semiconductors Product specification Dual 2-input exclusive-OR gate 74LVC2G86 FEATURES DESCRIPTION • Wide supply voltage range from 1.65 to 5.5 V


    Original     		PDF 74LVC2G86 74LVC2G86 SCA75 R20/01/pp12 11851 74LVC2G86DP

    Untitled

    Abstract: No abstract text available
    Text: 74AHC2G32; 74AHCT2G32 Dual 2-input OR gate Rev. 3 — 14 May 2013 Product data sheet 1. General description The 74AHC2G32; 74AHCT2G32 is a high-speed Si-gate CMOS device. The 74AHC2G32; 74AHCT2G32 provides two 2-input OR gates. 2. Features and benefits  Symmetrical output impedance


    Original     		PDF 74AHC2G32; 74AHCT2G32 74AHCT2G32 JESD22-A114E JESD22-A115-A JESD22-C101C 74AHC2G32DP

    ESD 141

    Abstract: No abstract text available
    Text: 74AUP2G125 Low-power dual buffer/line driver; 3-state Rev. 10 — 8 February 2013 Product data sheet 1. General description The 74AUP2G125 provides the dual non-inverting buffer/line driver with 3-state output. The 3-state output is controlled by the output enable input nOE . A HIGH level at pin nOE


    Original     		PDF 74AUP2G125 74AUP2G125 ESD 141

    Untitled

    Abstract: No abstract text available
    Text: 74LVC125A Quad buffer/line driver with 5 V tolerant input/outputs; 3-state Rev. 5 — 8 February 2012 Product data sheet 1. General description The 74LVC125A consists of four non-inverting buffers/line drivers with 3-state outputs nY that are controlled by the output enable input (nOE). A HIGH at nOE causes the


    Original     		PDF 74LVC125A 74LVC125A JESD8-B/JESD36

    74LVC1G08GV

    Abstract: 74LVC1G08 74LVC1G08GM 74LVC1G08GW
    Text: INTEGRATED CIRCUITS DATA SHEET 74LVC1G08 Single 2-input AND gate Product specification Supersedes data of 2002 Oct 02 2004 Sep 15 Philips Semiconductors Product specification Single 2-input AND gate 74LVC1G08 FEATURES DESCRIPTION • Wide supply voltage range from 1.65 V to 5.5 V


    Original     		PDF 74LVC1G08 74LVC1G08 JESD8B/JESD36 SCA76 R20/05/pp15 74LVC1G08GV 74LVC1G08GM 74LVC1G08GW

    NA32

    Abstract: No abstract text available
    Text: Multi-Layer Ceramic Chip Capacitor Array MNA Series Two or four multi-layer ceramic chip capacitors are fabricated on a single chip. Good solderability and small foot print reduce cost and space. #Dim enslons list Unit : mm MNA24 MNA22 Part No. MNA32 MNA34


    OCR Scan     		PDF MNA22 MNA24 MNA32 MNA34 A22/M A24/M MNA34 178mm NA32