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    BURST CONTROLLER COPROCESSOR Search Results

    BURST CONTROLLER COPROCESSOR Result Highlights (5)

    Part ECAD Model Manufacturer Description Download Buy
    MD8087/B Rochester Electronics LLC Math Coprocessor, CMOS Visit Rochester Electronics LLC Buy
    SSM6J808R Toshiba Electronic Devices & Storage Corporation MOSFET, P-ch, -40 V, -7 A, 0.035 Ohm@10V, TSOP6F, AEC-Q101 Visit Toshiba Electronic Devices & Storage Corporation
    SSM6K819R Toshiba Electronic Devices & Storage Corporation MOSFET, N-ch, 100 V, 10 A, 0.0258 Ohm@10V, TSOP6F, AEC-Q101 Visit Toshiba Electronic Devices & Storage Corporation
    SSM6K809R Toshiba Electronic Devices & Storage Corporation MOSFET, N-ch, 60 V, 6.0 A, 0.036 Ohm@10V, TSOP6F, AEC-Q101 Visit Toshiba Electronic Devices & Storage Corporation
    SSM6K504NU Toshiba Electronic Devices & Storage Corporation MOSFET, N-ch, 30 V, 9.0 A, 0.0195 Ohm@10V, UDFN6B, AEC-Q101 Visit Toshiba Electronic Devices & Storage Corporation

    BURST CONTROLLER COPROCESSOR Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    QFP PACKAGE thermal resistance

    Abstract: 80960SA 80960SB N80960SB1 65A176 AD928
    Text: 80960SB EMBEDDED 32-BIT MICROPROCESSOR WITH 16-BIT BURST DATA BUS • High-Performance Embedded Architecture ■ Built-in Interrupt Controller — 16 MIPS* Burst Execution at 16 MHz — 5 MIPS Sustained Execution at 16 MHz ■ 512-Byte On-Chip Instruction Cache


    Original     		PDF 80960SB 32-BIT 16-BIT 512-Byte 80960SA 80960SA 80960SB QFP PACKAGE thermal resistance N80960SB1 65A176 AD928

    treadmill motor controller

    Abstract: 82489dx free circuit diagram of treadmill 4g128 S82374EB Type B DMA pci 32 bit 5v dma controller chip 80386 microprocessor pin out diagram free circuit diagram of treadmill data transmission
    Text: 82374EB 82374SB EISA SYSTEM COMPONENT ESC Y Integrates EISA Compatible Bus Controller Translates Cycles Between EISA and ISA Bus Supports EISA Burst and Standard Cycles Supports ISA Zero Wait-State Cycles Supports Byte Assembly Disassembly for 8- 16- and 32-Bit


    Original     		PDF 82374EB 82374SB 32-Bit 82C37A IRQ13 82374EB) 82374SB) MASTER16 treadmill motor controller 82489dx free circuit diagram of treadmill 4g128 S82374EB Type B DMA pci 32 bit 5v dma controller chip 80386 microprocessor pin out diagram free circuit diagram of treadmill data transmission

    TA80960KB

    Abstract: 80960KA 80960KB 80960MC LAD1 12v
    Text: 80960KB 80960KB EMBEDDED 32-BIT MICROPROCESSOR WITH INTEGRATED FLOATING-POINT UNIT • High-Performance Embedded ■ Built-in Interrupt Controller Architecture — 25 MIPS Burst Execution at 25 MHz — 9.4 MIPS* Sustained Execution at 25 MHz ■ 512-Byte On-Chip Instruction Cache


    Original     		PDF 80960KB 32-BIT 512-Byte 132-Lead 80960KB TA80960KB 80960KA 80960MC LAD1 12v

    GT-64011

    Abstract: 79R3715 R4650 R4700 GT64010 Galileo Technology
    Text: Support Components Galileo Technology, Inc. Galileo-2 Secondary Cache Module For R4600, R4700 CPUs Standard Features ❏ Large secondary cache on-board - 512Kbytes or 256Kbytes ❏ 50Mhz bus frequency support ❏ Write-through, direct-mapped ❏ Zero wait-states to the first word


    Original     		PDF R4600, R4700 512Kbytes 256Kbytes 50Mhz GT-64010 GT-64012 R4600/RE* QS3383 32Kx18 GT-64011 79R3715 R4650 GT64010 Galileo Technology

    Untitled

    Abstract: No abstract text available
    Text:                ! ! Version 1.1 November 1999 2975 Stender Way, Santa Clara, California 95054 Telephone: 800 345-7015 • TWX: 910-338-2070 • FAX: (408) 492-8674 Printed in U.S.A.


    Original     		PDF

    16550 uart timing diagram

    Abstract: cold call sheet for estate agent RC32364
    Text:      1 RC32134 Device Overview Introduction .1-1 Block diagram .1-1


    Original     		PDF RC32134 16550 uart timing diagram cold call sheet for estate agent RC32364

    Untitled

    Abstract: No abstract text available
    Text: in tj 80960SB EMBEDDED 32-BIT MICROPROCESSOR WITH 16-BIT BURST DATA BUS • High-Performance Embedded Architecture — 16 MIPS* Burst Execution at 16 MHz — 5 MIPS Sustained Execution at 16 MHz ■ Built-In Interrupt Controller — 4 Direct Interrupt Pins


    OCR Scan     		PDF 80960SB 32-BIT 16-BIT 512-Byte 16-Bit 8096SA 4fl2bl75

    n80960sb

    Abstract: No abstract text available
    Text: in tj 80960SB EMBEDDED 32-BIT MICROPROCESSOR WITH 16-BIT BURST DATA BUS • High-Performance Embedded Architecture — 16 MIPS* Burst Execution at 16 MHz — 5 MIPS Sustained Execution at 16 MHz ■ Built-In Interrupt Controller — 4 Direct Interrupt Pins


    OCR Scan     		PDF 80960SB 32-BIT 16-BIT 512-Byte 16-Bit 8096SA MflEbl75 n80960sb

    pinout 80386

    Abstract: No abstract text available
    Text: MOSEL MS441 Cache Controller PRELIMINARY SimulCache chipset FEATURES DESCRIPTION • High Performance Cache Controller optimized for 486 Secondary cache or 386 Primary cache applications • Integrates two 386/486 bus controllers in combination with Dual Port Burst Memories for Concurrent Write


    OCR Scan     		PDF MS441 MS443 PID070A pinout 80386

    Untitled

    Abstract: No abstract text available
    Text: in te i 80960SA/80960SB EMBEDDED 32-BIT PROCESSORS WITH 16-BIT BURST DATA BUS High-Performance Embedded Architecture — 16 MIPS Burst Execution at 16 MHz — 5 MIPS* Sustained Execution at 16 MHz Built-In Interrupt Controller — 4 Direct Interrupt Pins — 32 Priority Levels 256 Vectors


    OCR Scan     		PDF 80960SA/80960SB 32-BIT 16-BIT 80960SB 512-Byte

    BA021

    Abstract: No abstract text available
    Text: M82389 MESSAGE PASSING COPROCESSOR A MULTIBUS II BUS INTERFACE CONTROLLER Military u Highly Integrated VLSI Device • High Performance Coprocessing Functions — Offloads CPU for Communication and Bus Interfacing — 40 Megabytes/Sec Burst Transfer Speed


    OCR Scan     		PDF M82389 32-Byte 149-Pin 164-Lead CSM/002 BA021

    Untitled

    Abstract: No abstract text available
    Text: AT40491/2 Features • Two-Chip PC/AT Compatible Chip Set for 80486 Based Systems of up to 33 MHz AT40491 System Controller AT40492 Data Buffer Controller Two 160-Pin Quad Flatpacks, 1-Micron CMOS Process On-Chip Support For Direct-mapped Copy-back Cache Supports 2,1,1,1 and 3,1,1,1 Cache Burst Cycles


    OCR Scan     		PDF AT40491/2 AT40491 AT40492 160-Pin 16-bit. AT40491/2 AT40206 AT40491-25 AT40492-25

    Untitled

    Abstract: No abstract text available
    Text: AT40281 Features • • • • • • • • • • • • One-Chip PC/AT Compatible Core Logic Controller for 80386SX Systems operating up to 33 MHz One 160-Pln Quad Flatpack, 1-Micron CMOS Technology CPU Interlace and ISA Bus Control Direct Mapped Posted Write Cache Controller with Burst Cache Fill


    OCR Scan     		PDF AT40281 80386SX 160-Pln 386SX AT40281 AT40281-16

    Untitled

    Abstract: No abstract text available
    Text: 80960KB EMBEDDED 32-BIT MICROPROCESSOR WITH INTEGRATED FLOATING POINT UNIT High-Performance Embedded Architecture — 25 MIPS Burst Execution at 25 MHz — 9.4 MIPS* Sustained Execution at 25 MHz Built-In Interrupt Controller — 31 Priority Levels, 256 Vectors


    OCR Scan     		PDF 80960KB 32-BIT 512-Byte 132-Lead 80960KB 4fl2bl75 01bb514

    Untitled

    Abstract: No abstract text available
    Text: intJ. 82374EB EISA SYSTEM COMPONENT ESC • Integrates EISA Compatible Bus Controller — Translates Cycles between EISA and ISA Bus — Supports EISA Burst and Standard Cycles — Supports ISA No Walt State Cycles — Supports Byte Assembly/ Disassembly for 8-, 16- and 32-Bit


    OCR Scan     		PDF 82374EB 32-Bit 82C37A

    dma controller chip

    Abstract: No abstract text available
    Text: in tj, 82374EB EISA SYSTEM COMPONENT ESC • Integrates EISA Compatible Bus Controller — Translates Cycles between EISA and ISA Bus — Supports EISA Burst and Standard Cycles — Supports ISA No Wait State Cycles — Supports Byte Assembly/ Disassembly for 8-, 16- and 32-Bit


    OCR Scan     		PDF 82374EB 32-Bit 82C37A dma controller chip

    82374EB/82374SB

    Abstract: No abstract text available
    Text: Ä I W Ä 1 OMIF ISBM!rD@M in tei 82374EB EISA SYSTEM COMPONENT ESC Integrates EISA Compatible Bus Controller — Translates Cycles between EISA and ISA Bus — Supports EISA Burst and Standard Cycles — Supports ISA No Wait State Cycles — Supports Byte Assembly/


    OCR Scan     		PDF 82374EB 32-Bit MASTER16# 82374EB/82374SB

    Scatter-Gather

    Abstract: No abstract text available
    Text: intel. DMP@K iälÄ¥D KI 82374EB/82374SB EISA SYSTEM COMPONENT (ESC • Integrates EISA Compatible Bus Controller — Translates Cycles Between EISA and ISA Bus — Supports EISA Burst and Standard Cycles — Supports ISA Zero Walt-State Cycles — Supports Byte Assembly/


    OCR Scan     		PDF 82374EB/82374SB Scatter-Gather

    Untitled

    Abstract: No abstract text available
    Text: 82307 DMA/Micro Channel ARBITRATION CONTROLLER • 8 Channel DMA Controller 8/ 16-Bit ■ Integrated Central Arbitration Control Point ■ Refresh Address Generation/Cycling ■ Numerics Co-processor Interface ■ Address Decoding — Numeric Coprocessor


    OCR Scan     		PDF 16-Bit) 132-Pin

    Untitled

    Abstract: No abstract text available
    Text: P[R3 [D IU) ST [p^EWOH in te i 82961 KD PRINTER COPROCESSOR High Performance Printer Coprocessor* — Direct Interface to Intel’s i960 KA or KB* 32-Bit Embedded Processors Direct Generic Printer Engine Interface — TEC, Canon, Ricoh, Okidata and Ink


    OCR Scan     		PDF 32-Bit 82961KD 82961KD

    ink cartridge electrical pinout

    Abstract: canon cartridge ic I0A10 canon ink cartridge chip ink cartridge chip 8296 intel
    Text: ra @ P y Y in te ! IP G ^ E W D IW 82961KD PRINTER COPROCESSOR High Performance Printer Coprocessor* — Direct Interface to Intel’s i960 KA or KB* 32-Bit Embedded Processors Direct Generic Printer Engine Interface — TEC, Canon, Ricoh, Okidata and Ink


    OCR Scan     		PDF 82961KD 32-Bit 82961KD ink cartridge electrical pinout canon cartridge ic I0A10 canon ink cartridge chip ink cartridge chip 8296 intel

    weitek

    Abstract: weitek 4167 chipset for 486 486 system bus 80386 memory
    Text: baSBBTl DDG17Db DS4 S4E » MOSEL IMO VI MS441 Cache Controller PRELIMINARY SimulCache chipset MO S E L - VITELIC FEATURES DESCRIPTION • High Performance Cache Controller optimized for 486 Secondary cache or 386 Primary cache applications • Integrates two 386/486 bus controllers in combination


    OCR Scan     		PDF DDG17Db MS441 MS443 PID070A 0GG17D7 MS441 T-52-33-21 weitek weitek 4167 chipset for 486 486 system bus 80386 memory

    BCR16

    Abstract: No abstract text available
    Text: PRELIMINARY AMD£I Am79C965 PCnet -32 Single-Chip 32-Bit Ethernet Controller DISTINCTIVE CHARACTERISTICS • Single-chip Ethernet controller for 486 and Video Electronics Standards Association VESA local buses ■ ■ Supports ISO 8802-3 (IEEE/ANSI 802.3) and


    OCR Scan     		PDF Am79C965 32-Bit 136-byte 128-byte Am486â 80C186 80C186 BCR16

    Programmable logic controller

    Abstract: No abstract text available
    Text: AT40493/392 Features • • • • • • • • • • • • • • • • • • • Two-Chip PC/AT Compatible Chip Set for 80486 Based Systems Operating up to 50 MHz AT40493 System and Cache Controller AT40392 Data Buffer Controller Two 160-Pin Quad Flatpacks


    OCR Scan     		PDF AT40493/392 AT40493 AT40392 160-Pin AT40493-25 AT40392-25 AT40493-33 Programmable logic controller