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    BURST CONTROLLER COPROCESSOR Search Results

    BURST CONTROLLER COPROCESSOR Result Highlights (5)

    Part ECAD Model Manufacturer Description Download Buy
    SSM6J808R Toshiba Electronic Devices & Storage Corporation MOSFET, P-ch, -40 V, -7 A, 0.035 Ohm@10V, TSOP6F, AEC-Q101 Visit Toshiba Electronic Devices & Storage Corporation
    SSM6K819R Toshiba Electronic Devices & Storage Corporation MOSFET, N-ch, 100 V, 10 A, 0.0258 Ohm@10V, TSOP6F, AEC-Q101 Visit Toshiba Electronic Devices & Storage Corporation
    SSM6K809R Toshiba Electronic Devices & Storage Corporation MOSFET, N-ch, 60 V, 6.0 A, 0.036 Ohm@10V, TSOP6F, AEC-Q101 Visit Toshiba Electronic Devices & Storage Corporation
    SSM6K504NU Toshiba Electronic Devices & Storage Corporation MOSFET, N-ch, 30 V, 9.0 A, 0.0195 Ohm@10V, UDFN6B, AEC-Q101 Visit Toshiba Electronic Devices & Storage Corporation
    SSM3K361R Toshiba Electronic Devices & Storage Corporation MOSFET, N-ch, 100 V, 3.5 A, 0.069 Ohm@10V, SOT-23F, AEC-Q101 Visit Toshiba Electronic Devices & Storage Corporation

    BURST CONTROLLER COPROCESSOR Datasheets Context Search

    Catalog Datasheet MFG & Type Document Tags PDF

    QFP PACKAGE thermal resistance

    Abstract: 65a176 AD427 80960SA 80960SB x80960SB 272207 D010D
    Text: 80960SB EMBEDDED 32-BIT MICROPROCESSOR WITH 16-BIT BURST DATA BUS • High-Performance Embedded Architecture ■ Built-in Interrupt Controller — 16 MIPS* Burst Execution at 16 MHz — 5 MIPS Sustained Execution at 16 MHz ■ 512-Byte On-Chip Instruction Cache


    Original     		80960SB 32-BIT 16-BIT 512-Byte 80960SA 80960SA 80960SB QFP PACKAGE thermal resistance 65a176 AD427 x80960SB 272207 D010D PDF

    QFP PACKAGE thermal resistance

    Abstract: 80960SA 80960SB N80960SB1 65A176 AD928
    Text: 80960SB EMBEDDED 32-BIT MICROPROCESSOR WITH 16-BIT BURST DATA BUS • High-Performance Embedded Architecture ■ Built-in Interrupt Controller — 16 MIPS* Burst Execution at 16 MHz — 5 MIPS Sustained Execution at 16 MHz ■ 512-Byte On-Chip Instruction Cache


    Original     		80960SB 32-BIT 16-BIT 512-Byte 80960SA 80960SA 80960SB QFP PACKAGE thermal resistance N80960SB1 65A176 AD928 PDF

    treadmill motor controller

    Abstract: 82489dx free circuit diagram of treadmill 4g128 S82374EB Type B DMA pci 32 bit 5v dma controller chip 80386 microprocessor pin out diagram free circuit diagram of treadmill data transmission
    Text: 82374EB 82374SB EISA SYSTEM COMPONENT ESC Y Integrates EISA Compatible Bus Controller Translates Cycles Between EISA and ISA Bus Supports EISA Burst and Standard Cycles Supports ISA Zero Wait-State Cycles Supports Byte Assembly Disassembly for 8- 16- and 32-Bit


    Original     		82374EB 82374SB 32-Bit 82C37A IRQ13 82374EB) 82374SB) MASTER16 treadmill motor controller 82489dx free circuit diagram of treadmill 4g128 S82374EB Type B DMA pci 32 bit 5v dma controller chip 80386 microprocessor pin out diagram free circuit diagram of treadmill data transmission PDF

    TA80960KB

    Abstract: LAD1 5V Intel 80960kb programmers reference 80960KA 80960KB 80960MC Intel 80960kb
    Text: 80960KB 80960KB EMBEDDED 32-BIT MICROPROCESSOR WITH INTEGRATED FLOATING-POINT UNIT • High-Performance Embedded ■ Built-in Interrupt Controller Architecture — 25 MIPS Burst Execution at 25 MHz — 9.4 MIPS* Sustained Execution at 25 MHz ■ 512-Byte On-Chip Instruction Cache


    Original     		80960KB 32-BIT 512-Byte 132-Lead 80960KB TA80960KB LAD1 5V Intel 80960kb programmers reference 80960KA 80960MC Intel 80960kb PDF

    TA80960kb

    Abstract: NG80960KB-25 80960KA 80960KB 80960MC
    Text: 80960KB 80960KB EMBEDDED 32-BIT MICROPROCESSOR WITH INTEGRATED FLOATING-POINT UNIT • High-Performance Embedded ■ Built-in Interrupt Controller Architecture — 25 MIPS Burst Execution at 25 MHz — 9.4 MIPS* Sustained Execution at 25 MHz ■ 512-Byte On-Chip Instruction Cache


    Original     		80960KB 32-BIT 512-Byte 132-Lead 80960KB TA80960kb NG80960KB-25 80960KA 80960MC PDF

    TA80960KB

    Abstract: 80960KA 80960KB 80960MC LAD1 12v
    Text: 80960KB 80960KB EMBEDDED 32-BIT MICROPROCESSOR WITH INTEGRATED FLOATING-POINT UNIT • High-Performance Embedded ■ Built-in Interrupt Controller Architecture — 25 MIPS Burst Execution at 25 MHz — 9.4 MIPS* Sustained Execution at 25 MHz ■ 512-Byte On-Chip Instruction Cache


    Original     		80960KB 32-BIT 512-Byte 132-Lead 80960KB TA80960KB 80960KA 80960MC LAD1 12v PDF

    canon printer controller

    Abstract: canon cartridge chip 8296 simm 72 dram 82961KD
    Text: PRINTERS INTEL CORPORATION iLASER961KD Laser Printer Controller Design Package • ■ ■ ■ ■ ■ ■ ■ ■ 20 MHz System Speed 4 MB of Interleaved ROM Program Memory; Burst Access 3, 0, 2, 0 Wait-State Optional 4 MB of Non-Interleaved Flash Memory for Additional


    Original     		iLASER961KD i960/82961KD 82961KD. 72-pin R-S232 canon printer controller canon cartridge chip 8296 simm 72 dram 82961KD PDF

    Untitled

    Abstract: No abstract text available
    Text: in tj 80960SB EMBEDDED 32-BIT MICROPROCESSOR WITH 16-BIT BURST DATA BUS • High-Performance Embedded Architecture — 16 MIPS* Burst Execution at 16 MHz — 5 MIPS Sustained Execution at 16 MHz ■ Built-In Interrupt Controller — 4 Direct Interrupt Pins


    OCR Scan     		80960SB 32-BIT 16-BIT 512-Byte 16-Bit 8096SA 4fl2bl75 PDF

    n80960sb

    Abstract: No abstract text available
    Text: in tj 80960SB EMBEDDED 32-BIT MICROPROCESSOR WITH 16-BIT BURST DATA BUS • High-Performance Embedded Architecture — 16 MIPS* Burst Execution at 16 MHz — 5 MIPS Sustained Execution at 16 MHz ■ Built-In Interrupt Controller — 4 Direct Interrupt Pins


    OCR Scan     		80960SB 32-BIT 16-BIT 512-Byte 16-Bit 8096SA MflEbl75 n80960sb PDF

    486 system bus

    Abstract: cache controller bus architecture 80386 weitek 4167 80386 cache architecture of 80486 MS441 MS443 386 chip set bus ARCHITECTURE OF 80386 data bus, control bus
    Text: MOSEL MS441 Cache Controller PRELIMINARY SimulCache chipset FEATURES DESCRIPTION • High Performance Cache Controller optimized for 486 Secondary cache or 386 Primary cache applications • Integrates two 386/486 bus controllers in combination with Dual Port Burst Memories for Concurrent Write


    OCR Scan     		MS441 MS443 PID070A 486 system bus cache controller bus architecture 80386 weitek 4167 80386 cache architecture of 80486 386 chip set bus ARCHITECTURE OF 80386 data bus, control bus PDF

    pinout 80386

    Abstract: No abstract text available
    Text: MOSEL MS441 Cache Controller PRELIMINARY SimulCache chipset FEATURES DESCRIPTION • High Performance Cache Controller optimized for 486 Secondary cache or 386 Primary cache applications • Integrates two 386/486 bus controllers in combination with Dual Port Burst Memories for Concurrent Write


    OCR Scan     		MS441 MS443 PID070A pinout 80386 PDF

    Untitled

    Abstract: No abstract text available
    Text: in te i 80960SA/80960SB EMBEDDED 32-BIT PROCESSORS WITH 16-BIT BURST DATA BUS High-Performance Embedded Architecture — 16 MIPS Burst Execution at 16 MHz — 5 MIPS* Sustained Execution at 16 MHz Built-In Interrupt Controller — 4 Direct Interrupt Pins — 32 Priority Levels 256 Vectors


    OCR Scan     		80960SA/80960SB 32-BIT 16-BIT 80960SB 512-Byte PDF

    386SX

    Abstract: 80386SX AT40281-16 DDD5735 isa pin diagram block diagram of bios
    Text: AT40281 Features • One-Chip PC/AT Compatible Core Logic Controller for 80386SX Systems operating up to 33 MHz One 160-Pin Quad Flatpack, 1-Micron CMOS Technology CPU Interlace and ISA Bus Control Direct Mapped Posted Write Cache Controller with Burst Cache Fill


    OCR Scan     		AT40281 80386SX 160-Pin 386SX AT4028Pin 1D7M17? DDD5735 AT40281-16 isa pin diagram block diagram of bios PDF

    BA021

    Abstract: No abstract text available
    Text: M82389 MESSAGE PASSING COPROCESSOR A MULTIBUS II BUS INTERFACE CONTROLLER Military u Highly Integrated VLSI Device • High Performance Coprocessing Functions — Offloads CPU for Communication and Bus Interfacing — 40 Megabytes/Sec Burst Transfer Speed


    OCR Scan     		M82389 32-Byte 149-Pin 164-Lead CSM/002 BA021 PDF

    intel 80486 architecture

    Abstract: 80486 microprocessor features 80486 architecture architecture of 80486 microprocessor 80486 subsystem design 80486 microprocessor architecture of 80486 processor intel 80486 80486 set 80486 interface
    Text: Product Brief IVIOSEL _ MS82C440 MAY 1990 Cache Chipset for 80486 Systems FEATURES Highly integrated VLSI components offer complete solution for secondary cache for 80486 systems - MS82C441 Cache Controller - MS82C442 Expansion Tag RAM - MS82C443 Burst RAM


    OCR Scan     		MS82C440 MS82C441 MS82C442 MS82C443 PID037 intel 80486 architecture 80486 microprocessor features 80486 architecture architecture of 80486 microprocessor 80486 subsystem design 80486 microprocessor architecture of 80486 processor intel 80486 80486 set 80486 interface PDF

    cartridges epson

    Abstract: laser interrupt counter 16550 uart timing General Purpose Mask Programmable ROM R3041
    Text: Integrated Device Technology, Inc. LASER PRINTER Integrated System Controller for IDT R30xx RISController Family with Adobe Frame Buffer Compression FEATURES: IDT79R3740 ADVANCE DATA - Supports burst ROMs Programmable I/O ports provide glue-less interface to


    OCR Scan     		R30xx IDT79R3740 R3041â R3051â R3052â R3071â R3081â 33MHz P1284 cartridges epson laser interrupt counter 16550 uart timing General Purpose Mask Programmable ROM R3041 PDF

    Untitled

    Abstract: No abstract text available
    Text: AT40281 Features • • • • • • • • • • • • One-Chip PC/AT Compatible Core Logic Controller for 80386SX Systems operating up to 33 MHz One 160-Pln Quad Flatpack, 1-Micron CMOS Technology CPU Interlace and ISA Bus Control Direct Mapped Posted Write Cache Controller with Burst Cache Fill


    OCR Scan     		AT40281 80386SX 160-Pln 386SX AT40281 AT40281-16 PDF

    atmel 924

    Abstract: 80386SX core logic
    Text: AT40281 Features • • • • • • • • • • • • One-Chip PC/AT Compatible Core Logic Controller for 80386SX Systems operating up to 33 MHz One 160-Pin Quad Flatpack, 1-Micron CMOS Technology CPU Interface and ISA Bus Control Direct Mapped Posted Write Cache Controller with Burst Cache Fill


    OCR Scan     		AT40281 80386SX 160-Pin 386SX AT40281 AT40206IPC atmel 924 80386SX core logic PDF

    Untitled

    Abstract: No abstract text available
    Text: AT40281 Features • • • • • • • • • • • • One-Chip PC/AT Compatible Core Logic Controller for 80386SX Systems operating up to 33 MHz One 160-Pin Quad Flatpack, 1-Micron CMOS Technology CPU Interface and ISA Bus Control Direct Mapped Posted Write Cache Controller with Burst Cache Fill


    OCR Scan     		AT40281 80386SX 160-Pin 386SX AT40281ler AT40206IPC AT40281 AT40281-16 PDF

    Untitled

    Abstract: No abstract text available
    Text: 80960KB EMBEDDED 32-BIT MICROPROCESSOR WITH INTEGRATED FLOATING POINT UNIT High-Performance Embedded Architecture — 25 MIPS Burst Execution at 25 MHz — 9.4 MIPS* Sustained Execution at 25 MHz Built-In Interrupt Controller — 31 Priority Levels, 256 Vectors


    OCR Scan     		80960KB 32-BIT 512-Byte 132-Lead 80960KB 4fl2bl75 01bb514 PDF

    Untitled

    Abstract: No abstract text available
    Text: 80960KB EMBEDDED 32-BIT MICROPROCESSOR WITH INTEGRATED FLOATING POINT UNIT • High-Performance Embedded Architecture — 25 MIPS Burst Execution at 25 MHz — 9.4 MIPS* Sustained Execution at 25 MHz ■ Built-In Interrupt Controller — 31 Priority Levels, 256 Vectors


    OCR Scan     		80960KB 32-BIT 512-Byte 132-Lead 80960KB 4fl2bl75 PDF

    Untitled

    Abstract: No abstract text available
    Text: intJ. 82374EB EISA SYSTEM COMPONENT ESC • Integrates EISA Compatible Bus Controller — Translates Cycles between EISA and ISA Bus — Supports EISA Burst and Standard Cycles — Supports ISA No Walt State Cycles — Supports Byte Assembly/ Disassembly for 8-, 16- and 32-Bit


    OCR Scan     		82374EB 32-Bit 82C37A PDF

    VL82C480

    Abstract: weitek pcs weitek 4167 VL82C480-FC VL82C113 weitek "bus steering logic" vl82c10 "Lookaside Cache"
    Text: AUG i 2 1993 V L S I Technology inc 'P : 7L _ VL82C480 486 SYSTEM/CACHE/ISA BUS CONTROLLER FEATURES - Page Mode DRAM access Two-way interleave support Programmable RAS#/CAS# timing Burst read and write support Parity generation/checking for on­ board DRAM


    OCR Scan     		VL82C480 486-based 82C37A 74LS612 82C59A 82C54 VL82C480 weitek pcs weitek 4167 VL82C480-FC VL82C113 weitek "bus steering logic" vl82c10 "Lookaside Cache" PDF

    dma controller chip

    Abstract: No abstract text available
    Text: in tj, 82374EB EISA SYSTEM COMPONENT ESC • Integrates EISA Compatible Bus Controller — Translates Cycles between EISA and ISA Bus — Supports EISA Burst and Standard Cycles — Supports ISA No Wait State Cycles — Supports Byte Assembly/ Disassembly for 8-, 16- and 32-Bit


    OCR Scan     		82374EB 32-Bit 82C37A dma controller chip PDF