CY28351 Search Results

CY28351 Datasheets (6)

Part	ECAD Model	Manufacturer	Description	Curated	Datasheet Type	PDF
CY28351		Cypress Semiconductor	Differential Clock Buffer/Driver DDR400- and DDR333-Compliant		Original	PDF
CY28351		Spectra Linear	Differential Clock Buffer/Driver		Original	PDF
CY28351OC		Cypress Semiconductor	Differential Clock Buffer/Driver DDR400- and DDR333-Compliant		Original	PDF
CY28351OC		Spectra Linear	Differential Clock Buffer/Driver		Original	PDF
CY28351OCT		Cypress Semiconductor	Differential Clock Buffer/Driver DDR400- and DDR333-Compliant		Original	PDF
CY28351OCT		Spectra Linear	Differential Clock Buffer/Driver		Original	PDF

CY28351 Datasheets Context Search

Catalog Datasheet	MFG & Type	Document Tags	PDF
CY28351OC Abstract: No abstract text available Text: CY28351-400 Differential Clock Buffer/Driver Features Description • Supports 333-MHz and 400-MHz DDR SDRAM • 60 – 273-MHz operating frequency • Phase-locked loop PLL clock distribution for double data rate synchronous DRAM applications • Distributes one clock input to ten differential outputs	Original	CY28351-400 333-MHz 400-MHz 273-MHz 48-pin CY28351OC	PDF
CY28351 Abstract: CY28351OC CY28351OCT Text: CY28351 Differential Clock Buffer/Driver DDR400- and DDR333-Compliant Features Description • Supports 333-MHz and 400-MHz DDR SDRAM • 60- – 200-MHz operating frequency • Phase-locked loop PLL clock distribution for double data rate synchronous DRAM applications	Original	CY28351 DDR400- DDR333-Compliant 333-MHz 400-MHz 200-MHz 48-pin CY28351 CY28351OC CY28351OCT	PDF
CY28351 Abstract: CY28351OC CY28351OCT Text: CY28351 Differential Clock Buffer/Driver Features Description • Supports 333-MHz and 400-MHz DDR SDRAM • 60- – 200-MHz operating frequency • Phase-locked loop PLL clock distribution for double data rate synchronous DRAM applications • Distributes one clock input to ten differential outputs	Original	CY28351 333-MHz 400-MHz 200-MHz 48-pin CY28351 CY28351OC CY28351OCT	PDF
CY28351 Abstract: CY28351OC CY28351OCT 127-01-1 Text: CY28351 Differential Clock Buffer/Driver DDR400- and DDR333-Compliant Features Description • Supports 333-MHz and 400-MHz DDR SDRAM • 60- – 200-MHz operating frequency • Phase-locked loop PLL clock distribution for double data rate synchronous DRAM applications	Original	CY28351 DDR400- DDR333-Compliant 333-MHz 400-MHz 200-MHz 48-pin CY28351 CY28351OC CY28351OCT 127-01-1	PDF
Untitled Abstract: No abstract text available Text: CY28351 Differential Clock Buffer/Driver Features Description • Phase-locked loop PLL clock distribution for double data rate synchronous DRAM applications • Distributes one clock input to ten differential outputs • External feedback pin (FBIN) is used to synchronize the	Original	CY28351 48-pin CY28351	PDF
CY28351 Abstract: CY28351OC CY28351OCT Text: CY28351 Differential Clock Buffer/Driver Features Description • Phase-locked loop PLL clock distribution for double data rate synchronous DRAM applications • Distributes one clock input to ten differential outputs • External feedback pin (FBIN) is used to synchronize the	Original	CY28351 48-pin CY28351 CY28351OC CY28351OCT	PDF
Untitled Abstract: No abstract text available Text: CY28351 Differential Clock Buffer/Driver Features Description • Supports 333-MHz and 400-MHz DDR SDRAM • 60- – 200-MHz operating frequency • Phase-locked loop PLL clock distribution for double data rate synchronous DRAM applications • Distributes one clock input to ten differential outputs	Original	CY28351 333-MHz 400-MHz 200-MHz 48-pin	PDF