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    CY28351OCT Search Results

    CY28351OCT Datasheets (2)

    Part ECAD Model Manufacturer Description Curated Datasheet Type PDF
    CY28351OCT Cypress Semiconductor Differential Clock Buffer/Driver DDR400- and DDR333-Compliant Original PDF
    CY28351OCT Spectra Linear Differential Clock Buffer/Driver Original PDF

    CY28351OCT Datasheets Context Search

    Catalog Datasheet MFG & Type Document Tags PDF

    CY28351

    Abstract: CY28351OC CY28351OCT
    Text: CY28351 Differential Clock Buffer/Driver DDR400- and DDR333-Compliant Features Description • Supports 333-MHz and 400-MHz DDR SDRAM • 60- – 200-MHz operating frequency • Phase-locked loop PLL clock distribution for double data rate synchronous DRAM applications


    Original     		CY28351 DDR400- DDR333-Compliant 333-MHz 400-MHz 200-MHz 48-pin CY28351 CY28351OC CY28351OCT PDF

    CY28351

    Abstract: CY28351OC CY28351OCT
    Text: CY28351 Differential Clock Buffer/Driver Features Description • Supports 333-MHz and 400-MHz DDR SDRAM • 60- – 200-MHz operating frequency • Phase-locked loop PLL clock distribution for double data rate synchronous DRAM applications • Distributes one clock input to ten differential outputs


    Original     		CY28351 333-MHz 400-MHz 200-MHz 48-pin CY28351 CY28351OC CY28351OCT PDF

    CY28351

    Abstract: CY28351OC CY28351OCT 127-01-1
    Text: CY28351 Differential Clock Buffer/Driver DDR400- and DDR333-Compliant Features Description • Supports 333-MHz and 400-MHz DDR SDRAM • 60- – 200-MHz operating frequency • Phase-locked loop PLL clock distribution for double data rate synchronous DRAM applications


    Original     		CY28351 DDR400- DDR333-Compliant 333-MHz 400-MHz 200-MHz 48-pin CY28351 CY28351OC CY28351OCT 127-01-1 PDF

    Untitled

    Abstract: No abstract text available
    Text: CY28351 Differential Clock Buffer/Driver Features Description • Phase-locked loop PLL clock distribution for double data rate synchronous DRAM applications • Distributes one clock input to ten differential outputs • External feedback pin (FBIN) is used to synchronize the


    Original     		CY28351 48-pin CY28351 PDF

    CY28351

    Abstract: CY28351OC CY28351OCT
    Text: CY28351 Differential Clock Buffer/Driver Features Description • Phase-locked loop PLL clock distribution for double data rate synchronous DRAM applications • Distributes one clock input to ten differential outputs • External feedback pin (FBIN) is used to synchronize the


    Original     		CY28351 48-pin CY28351 CY28351OC CY28351OCT PDF

    Untitled

    Abstract: No abstract text available
    Text: CY28351 Differential Clock Buffer/Driver Features Description • Supports 333-MHz and 400-MHz DDR SDRAM • 60- – 200-MHz operating frequency • Phase-locked loop PLL clock distribution for double data rate synchronous DRAM applications • Distributes one clock input to ten differential outputs


    Original     		CY28351 333-MHz 400-MHz 200-MHz 48-pin PDF