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Cypress Semiconductor CY28352OC DDR ZDB Buffer for SiS Chipset '
Distributors	Part	Package	Stock	Lead Time	Min Order Qty	Price	Buy
Rochester Electronics	CY28352OC		91		1	1 $2.63 10 $2.63 100 $2.47 1000 $2.24 10000 $2.24	Buy Now

CY28352OC Datasheets (5)

Part	ECAD Model	Manufacturer	Description	Curated	Datasheet Type	PDF
CY28352OC		Cypress Semiconductor	Differential Clock Buffer/Driver DDR400- and DDR333-Compliant		Original	PDF
CY28352OC		Cypress Semiconductor	Differential Clock Buffer/Driver		Original	PDF
CY28352OCT		Cypress Semiconductor	Differential Clock Buffer/Driver DDR400- and DDR333-Compliant		Original	PDF
CY28352OCT		Cypress Semiconductor	Differential Clock Buffer/Driver		Original	PDF
CY28352OCT		Spectra Linear	Differential Clock Buffer/Driver DDR400- and DDR333-Compliant		Original	PDF

CY28352OC Datasheets Context Search

Catalog Datasheet	MFG & Type	Document Tags	PDF
Untitled Abstract: No abstract text available Text: CY28352 Differential Clock Buffer/Driver Features Description • Phase-locked loop PLL clock distribution for double data rate synchronous DRAM applications • Distributes one clock input to six differential outputs • External feedback pin FBIN is used to synchronize	Original	CY28352 28-pin CY28352	PDF
CY28352 Abstract: CY28352OC CY28352OCT CY28352OXC Text: CY28352 Differential Clock Buffer/Driver DDR400and DDR333-Compliant Features Description • Supports 333-MHz and 400-MHz DDR SDRAM • 60- – 200-MHz operating frequency This PLL clock buffer is designed for 2.5-VDD and 2.5-AVDD operation and differential output levels.	Original	CY28352 DDR400and DDR333-Compliant 333-MHz 400-MHz 200-MHz CY28352 DDR400- DDR333-Compliant, CY28352OC CY28352OCT CY28352OXC	PDF
CY28352OC Abstract: DDR400 Text: CY28352-400 Differential Clock Buffer/Driver DDR400 and DDR333-Compliant Features Description • Supports 333-MHz and 400-MHz DDR SDRAM • 60–273-MHz operating frequency This PLL clock buffer is designed for 2.6VDD and 2.6AVDD operation and differential output levels.	Original	CY28352-400 DDR400 DDR333-Compliant 333-MHz 400-MHz 273-MHz CY28352OC	PDF
CY28352 Abstract: CY28352OC CY28352OCT CY28352OXC Text: CY28352 Differential Clock Buffer/Driver DDR400and DDR333-Compliant Features Description • Supports 333-MHz and 400-MHz DDR SDRAM • 60- – 200-MHz operating frequency This PLL clock buffer is designed for 2.5-VDD and 2.5-AVDD operation and differential output levels.	Original	CY28352 DDR400and DDR333-Compliant 333-MHz 400-MHz 200-MHz CY28352 DDR400- DDR333-Compliant, CY28352OC CY28352OCT CY28352OXC	PDF
47AB Abstract: SCD1U16V3KX BCB25 BC536 BC163 216t9 sis645dx foxconn WISTRON BC466 Text: CLK GEN TOUCAN2 DesKtop-CPU Northwood 2.2~3.06GHz ICS:ICS952004AG DDRBUF:ICS93732 3,4 5,6 VRAM2 FSB 533/400MHz K4D263238M-QC40 CRT 17 2.5V 200MHz/266MHz DDR 2 11,12,13 SiS962 24 CD-ROM AGP 4X W/RTC 15" MII LAN MAC PHY 20,21,22,23 1394 conn. Agere FW802A	Original	ICS952004AG ICS93732 06GHz K4D263238M-QC40 533/400MHz 200MHz/266MHz 47Y01 SiS645DX 66MHz 16bits/533MBs 47AB SCD1U16V3KX BCB25 BC536 BC163 216t9 foxconn WISTRON BC466	PDF
1g22SB Abstract: SB3211 BC741 SIS 648 SB315 CP2216 AMS1117 1104 BC246 RB342 diode sb315 Text: M A R G A I D K C O L B M E T S Y S D 3 K PCB LAYER High Speed DDR-SDRAM K4D263238A-GC36 Clock Gen CY28381 100MHz P.17,18 DeskTop CPU Northwood FSB 400/533MHz P.11 2.5V 266/333MHz P.19 275MHz P.5,6 P.3 DDR*2 CRT CONN Delay Buffer CY28352 2.5V 266/333MHz P.4	Original	CY28381 K4D263238A-GC36 100MHz 400/533MHz 275MHz 266/333MHz CY28352 NV18-PRO) 133MHz 1g22SB SB3211 BC741 SIS 648 SB315 CP2216 AMS1117 1104 BC246 RB342 diode sb315	PDF
CY28352 Abstract: CY28352OC CY28352OCT CY28352OXC Text: CY28352 Differential Clock Buffer/Driver DDR400- and DDR333-Compliant Features Description • Supports 333 MHz and 400-MHz DDR SDRAM • 60- 200 MHz operating frequency This PLL clock buffer is designed for 2.5-VDD and 2.5-AVDD operation and differential output levels.	Original	CY28352 DDR400- DDR333-Compliant 400-MHz CY28352 CY28352OC CY28352OCT CY28352OXC	PDF
CY28352 Abstract: CY28352OC CY28352OCT Text: CY28352 Differential Clock Buffer/Driver Features Description • Phase-locked loop PLL clock distribution for double data rate synchronous DRAM applications • Distributes one clock input to six differential outputs • External feedback pin FBIN is used to synchronize	Original	CY28352 28-pin CY28352 CY28352OC CY28352OCT	PDF
CY28352 Abstract: CY28352OC CY28352OCT DDR333 DDR400 Text: CY28352 Differential Clock Buffer/Driver DDR400- and DDR333 Compliant Features Description • Supports 333-MHz and 400-MHz DDR SDRAM • 60- – 200-MHz operating frequency • Phase-locked loop PLL clock distribution for double data rate synchronous DRAM applications	Original	CY28352 DDR400- DDR333 333-MHz 400-MHz 200-MHz 28-pin CY28352 CY28352OC CY28352OCT DDR400	PDF