CY28352OCT Search Results

CY28352OCT Datasheets (3)

Part	ECAD Model	Manufacturer	Description	Curated	Datasheet Type	PDF
CY28352OCT		Cypress Semiconductor	Differential Clock Buffer/Driver DDR400- and DDR333-Compliant		Original	PDF
CY28352OCT		Cypress Semiconductor	Differential Clock Buffer/Driver		Original	PDF
CY28352OCT		Spectra Linear	Differential Clock Buffer/Driver DDR400- and DDR333-Compliant		Original	PDF

CY28352OCT Datasheets Context Search

Catalog Datasheet	MFG & Type	Document Tags	PDF
Untitled Abstract: No abstract text available Text: CY28352 Differential Clock Buffer/Driver Features Description • Phase-locked loop PLL clock distribution for double data rate synchronous DRAM applications • Distributes one clock input to six differential outputs • External feedback pin FBIN is used to synchronize	Original	CY28352 28-pin CY28352	PDF
CY28352 Abstract: CY28352OC CY28352OCT CY28352OXC Text: CY28352 Differential Clock Buffer/Driver DDR400and DDR333-Compliant Features Description • Supports 333-MHz and 400-MHz DDR SDRAM • 60- – 200-MHz operating frequency This PLL clock buffer is designed for 2.5-VDD and 2.5-AVDD operation and differential output levels.	Original	CY28352 DDR400and DDR333-Compliant 333-MHz 400-MHz 200-MHz CY28352 DDR400- DDR333-Compliant, CY28352OC CY28352OCT CY28352OXC	PDF
CY28352 Abstract: CY28352OC CY28352OCT CY28352OXC Text: CY28352 Differential Clock Buffer/Driver DDR400and DDR333-Compliant Features Description • Supports 333-MHz and 400-MHz DDR SDRAM • 60- – 200-MHz operating frequency This PLL clock buffer is designed for 2.5-VDD and 2.5-AVDD operation and differential output levels.	Original	CY28352 DDR400and DDR333-Compliant 333-MHz 400-MHz 200-MHz CY28352 DDR400- DDR333-Compliant, CY28352OC CY28352OCT CY28352OXC	PDF
CY28352 Abstract: CY28352OC CY28352OCT CY28352OXC Text: CY28352 Differential Clock Buffer/Driver DDR400- and DDR333-Compliant Features Description • Supports 333 MHz and 400-MHz DDR SDRAM • 60- 200 MHz operating frequency This PLL clock buffer is designed for 2.5-VDD and 2.5-AVDD operation and differential output levels.	Original	CY28352 DDR400- DDR333-Compliant 400-MHz CY28352 CY28352OC CY28352OCT CY28352OXC	PDF
CY28352 Abstract: CY28352OC CY28352OCT Text: CY28352 Differential Clock Buffer/Driver Features Description • Phase-locked loop PLL clock distribution for double data rate synchronous DRAM applications • Distributes one clock input to six differential outputs • External feedback pin FBIN is used to synchronize	Original	CY28352 28-pin CY28352 CY28352OC CY28352OCT	PDF
CY28352 Abstract: CY28352OC CY28352OCT DDR333 DDR400 Text: CY28352 Differential Clock Buffer/Driver DDR400- and DDR333 Compliant Features Description • Supports 333-MHz and 400-MHz DDR SDRAM • 60- – 200-MHz operating frequency • Phase-locked loop PLL clock distribution for double data rate synchronous DRAM applications	Original	CY28352 DDR400- DDR333 333-MHz 400-MHz 200-MHz 28-pin CY28352 CY28352OC CY28352OCT DDR400	PDF