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    CY39165 Search Results

    CY39165 Datasheets (55)

    Part ECAD Model Manufacturer Description Curated Datasheet Type PDF
    CY39165V Cypress Semiconductor Development Software Original PDF
    CY39165V208-125NTC Cypress Semiconductor CPLD at FPGA Densities Original PDF
    CY39165V208-125NTC Cypress Semiconductor Delta39K ISR CPLD. Speed 125 MHz. Original PDF
    CY39165V208-125NTI Cypress Semiconductor Delta39K ISR CPLD. Speed 125 MHz. Original PDF
    CY39165V208-125NTI Cypress Semiconductor CPLD at FPGA Densities Original PDF
    CY39165V208-181NTC Cypress Semiconductor CPLD at FPGA Densities Original PDF
    CY39165V208-181NTC Cypress Semiconductor Delta39K ISR CPLD. Speed 181 MHz. Original PDF
    CY39165V208-83NTC Cypress Semiconductor CPLD at FPGA Densities Original PDF
    CY39165V208-83NTC Cypress Semiconductor Delta39K ISR CPLD. Speed 83 MHz. Original PDF
    CY39165V208-83NTI Cypress Semiconductor CPLD at FPGA Densities Original PDF
    CY39165V208-83NTI Cypress Semiconductor Delta39K ISR CPLD. Speed 83 MHz. Original PDF
    CY39165V256-125BBI Cypress Semiconductor Delta39K ISR CPLD. Speed 125 MHz. Original PDF
    CY39165V388-125MGC Cypress Semiconductor CPLD at FPGA Densities Original PDF
    CY39165V388-125MGC Cypress Semiconductor Delta39K ISR CPLD. Speed 125 MHz. Original PDF
    CY39165V388-125MGI Cypress Semiconductor CPLD at FPGA Densities Original PDF
    CY39165V388-181MGC Cypress Semiconductor Delta39K ISR CPLD. Speed 181 MHz. Original PDF
    CY39165V388-181MGC Cypress Semiconductor CPLD at FPGA Densities Original PDF
    CY39165V388-83MGC Cypress Semiconductor CPLD at FPGA Densities Original PDF
    CY39165V388-83MGC Cypress Semiconductor Delta39K ISR CPLD. Speed 83 MHz. Original PDF
    CY39165V388-83MGI Cypress Semiconductor CPLD at FPGA Densities Original PDF

    CY39165 Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    Untitled

    Abstract: No abstract text available
    Text: Delta39K ISR™ CPLD Family CPLDs at FPGA Densities™ Features • Carry-chain logic for fast and efficient arithmetic operations • Multiple I/O standards supported — LVCMOS 3.3/3.0/2.5/1.8V , LVTTL, 3.3V PCI, SSTL2 (I-II), SSTL3 (I-II), HSTL (I-IV), and GTL+


    Original     		PDF Delta39Kâ 64-bit 39K200-208EQFP 39K165 39K200 -233MHz Delta39K165Z 144-FBGA

    BGA and eQFP Package

    Abstract: BGA 256 PACKAGE thermal resistance fbga 12 x 12 thermal resistance
    Text: PRELIMINARY Delta39K Power Estimation and Thermal Management Summary This application note covers a brief explanation of the Delta39K™ Power Estimator spreadsheet, suggestions on reducing the overall power consumption of Delta39K designs, and use of forced airflow and heat-sinks to manage heat dissipation.


    Original     		PDF Delta39KTM Delta39K BGA and eQFP Package BGA 256 PACKAGE thermal resistance fbga 12 x 12 thermal resistance

    delta39k

    Abstract: No abstract text available
    Text: Delta39KTM and Quantum38KTM Single-Port Memory Introduction Channel and Cluster Memory The purpose of this application note is to provide instruction for all aspects of implementing synchronous/asynchronous Single-Port Random-Access-Memory SPRAM and Single-Port Read-Only-Memory (SPROM) in Delta39K and


    Original     		PDF Delta39KTM Quantum38KTM Delta39K Quantum38K

    8kx1 RAM

    Abstract: No abstract text available
    Text: Delta39K ISR™ CPLD Family PRELIMINARY CPLDs at FPGA Densities™ Features • Multiple I/O standards supported — LVCMOS 3.3/3.0/2.5/1.8V , LVTTL, 3.3V PCI, SSTL2 (I-II), SSTL3 (I-II), HSTL (I-IV), and GTL+ • Compatible with NOBL™, ZBT™, and QDR™ SRAMs


    Original     		PDF Delta39KTM 233-MHz MIL-STD-883" /JESD22A114-A 39K50 39K30 Delta39K 39K165/200 CY3LV002 CY3LV020. 8kx1 RAM

    39k200

    Abstract: CY39200V
    Text: Delta39K ISR™ CPLD Family PRELIMINARY CPLDs at FPGA Densities™ Features •Multiple I/O standards supported — LVCMOS 3.3/3.0/2.5/1.8V , LVTTL, 3.3V PCI, SSTL2 (I-II), SSTL3 (I-II), HSTL (I-IV), and GTL+ •Compatible with NOBL™, ZBT™, and QDR™ SRAMs


    Original     		PDF Delta39KTM 250-MHz 39k200 CY39200V

    CY39100V484B-125BBI

    Abstract: programmable slew rate control IO AT17LV010-10JI CY39030V256-125MBC IO1 5V 39K100 39K165 39K30 39K50 CY39100V208B-125NTC
    Text: Delta39K ISR™ CPLD Family CPLDs at FPGA Densities™ Features • Carry-chain logic for fast and efficient arithmetic operations • Multiple I/O standards supported — LVCMOS 3.3/3.0/2.5/1.8V , LVTTL, 3.3V PCI, SSTL2 (I-II), SSTL3 (I-II), HSTL (I-IV), and GTL+


    Original     		PDF Delta39KTM 66-MHz 64-bit 39K165 MG388 CY39030 -256FBGA CY39100V484B-125BBI programmable slew rate control IO AT17LV010-10JI CY39030V256-125MBC IO1 5V 39K100 39K30 39K50 CY39100V208B-125NTC

    39K100

    Abstract: 39K30 39K50
    Text: Delta39K ISR™ CPLD Family PRELIMINARY CPLDs at FPGA Densities™ Features — Clock polarity control at each register • Carry-chain logic for fast and efficient arithmetic operations • Multiple I/O standards supported — LVCMOS 3.3/3.0/2.5/1.8V , LVTTL, 3.3V PCI, SSTL2


    Original     		PDF Delta39KTM 64-bit 39K200-208EQFP 39K165 39K200 -233MHz Delta39K165Z 39K100 39K30 39K50

    CY39200V

    Abstract: No abstract text available
    Text: Delta39K ISR™ CPLD Family PRELIMINARY CPLDs at FPGA Densities™ •Multiple I/O standards supported — LVCMOS, LVTTL, 3.3V PCI, SSTL2 I-II , SSTL3 (I-II), HSTL (I-IV), and GTL+ •Compatible with NOBL™, ZBT™, and QDR™ SRAMs •Programmable slew rate control on each I/O pin


    Original     		PDF Delta39KTM NT208 51-85069-B 388-Lead MG388 256-Ball BB256/MB256 1-85108-A CY39200V

    Untitled

    Abstract: No abstract text available
    Text: PRELIMINARY Delta39K ISR™ CPLD Family—Pin Tables CPLDs at FPGA Densities™ Table 1. Pin Definition Table[1] Pin Name CCLK Config_Done Function Description Output Configuration Clock for serial interface with the external boot PROM Output Flag indicating that configuration is complete


    Original     		PDF Delta39KTM CY39165 CY39200 CY39100

    delta39k

    Abstract: 39K100 39K30 39K50
    Text: Delta39K ISR™ CPLD Family CPLDs at FPGA Densities™ Features • Carry-chain logic for fast and efficient arithmetic operations • Multiple I/O standards supported — LVCMOS 3.3/3.0/2.5/1.8V , LVTTL, 3.3V PCI, SSTL2 (I-II), SSTL3 (I-II), HSTL (I-IV), and GTL+


    Original     		PDF Delta39KTM 64-bit 39K165 MG388 CY39030 -256FBGA delta39k 39K100 39K30 39K50

    delta39k

    Abstract: 39K100 39K165 39K30 39K50 CY3LV010 CY39200V
    Text: Delta39K ISR™ CPLD Family PRELIMINARY CPLDs at FPGA Densities™ Features • Multiple I/O standards supported — LVCMOS 3.3/3.0/2.5/1.8V , LVTTL, 3.3V PCI, SSTL2 (I-II), SSTL3 (I-II), HSTL (I-IV), and GTL+ • Compatible with NOBL™, ZBT™, and QDR™ SRAMs


    Original     		PDF Delta39KTM 64-bit Delta39K 39K165/200 CY3LV002 CY3LV020. Delta39K. 39K100 39K165 39K30 39K50 CY3LV010 CY39200V

    CY39100V484-125BBI

    Abstract: "Single-Port RAM" delta39k
    Text: Delta39K ISR™ CPLD Family PRELIMINARY CPLDs at FPGA Densities™ •Multiple I/O standards supported — LVCMOS, LVTTL, 3.3V PCI, SSTL2 I-II , SSTL3 (I-II), HSTL (I-IV), and GTL+ •Compatible with NOBL™, ZBT™, and QDR™ SRAMs •Programmable slew rate control on each I/O pin


    Original     		PDF Delta39KTM CY39100V484-125BBI "Single-Port RAM" delta39k

    NT208

    Abstract: 1kx8 rom 250NTC
    Text: Delta39K ISR™ CPLD Family PRELIMINARY CPLDs at FPGA Densities™ •Carry-chain logic for fast and efficient arithmetic operations •Multiple I/O standards supported — LVCMOS 3.3/3.0/2.5/1.8V , LVTTL, 3.3V PCI, SSTL2 (I-II), SSTL3 (I-II), HSTL (I-IV), and GTL+


    Original     		PDF Delta39KTM 250-MHz NT208 1kx8 rom 250NTC