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    CY7C129 Price and Stock

    Rochester Electronics LLC CY7C1298F-133AC

    STANDARD SRAM, 64KX18, 4NS, CMOS
    Distributors Part Package Stock Lead Time Min Order Qty Price Buy
    DigiKey CY7C1298F-133AC Bulk 18
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    Rochester Electronics LLC CY7C1297H-133AXC

    IC SRAM 1MBIT PARALLEL 100TQFP
    Distributors Part Package Stock Lead Time Min Order Qty Price Buy
    DigiKey CY7C1297H-133AXC Tray 18
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    Rochester Electronics LLC CY7C1297S-133AXC

    IC SRAM 1MBIT PARALLEL 100TQFP
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    DigiKey CY7C1297S-133AXC Bag 18
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    Rochester Electronics LLC CY7C1292DV18-167BZC

    IC SRAM 9MBIT PAR 167MHZ 165FBGA
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    DigiKey CY7C1292DV18-167BZC Tray 13
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    Infineon Technologies AG CY7C1292DV18-167BZC

    IC SRAM 9MBIT PAR 167MHZ 165FBGA
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    DigiKey CY7C1292DV18-167BZC Tray 136
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    CY7C129 Datasheets (26)

    Part ECAD Model Manufacturer Description Curated Datasheet Type PDF
    CY7C129 Cypress Semiconductor RAM9 QDR-I/DDR-I/QDR-II/DDR- II Errata Original PDF
    CY7C1292DV18 Cypress Semiconductor 9-Mbit QDR- II SRAM 2-Word Burst Architecture Original PDF
    CY7C1292DV18-167BZC Cypress Semiconductor 9-Mbit QDR- II SRAM 2-Word Burst Architecture Original PDF
    CY7C1294DV18 Cypress Semiconductor 9-Mbit QDR- II SRAM 2-Word Burst Architecture Original PDF
    CY7C1294DV18-167BZC Cypress Semiconductor 9-Mbit QDR- II SRAM 2-Word Burst Architecture Original PDF
    CY7C1297A Cypress Semiconductor Memory : Sync SRAMs Original PDF
    CY7C1297A-50AC Cypress Semiconductor Memory : Sync SRAMs Original PDF
    CY7C1297A-66AC Cypress Semiconductor Memory : Sync SRAMs Original PDF
    CY7C1297F Cypress Semiconductor 1-Mb (64K x 18) Flow-Through Sync SRAM Original PDF
    CY7C1297F-117AC Cypress Semiconductor 1-Mb (64K x 18) Flow-Through Sync SRAM Original PDF
    CY7C1297H Cypress Semiconductor 1-Mbit (64K x 18) Flow-Through Sync SRAM Original PDF
    CY7C1297H-100AXC Cypress Semiconductor 1-Mbit (64K x 18) Flow-Through Sync SRAM Original PDF
    CY7C1297H-100AXI Cypress Semiconductor 1-Mbit (64K x 18) Flow-Through Sync SRAM Original PDF
    CY7C1297H-133AXC Cypress Semiconductor 1-Mbit (64K x 18) Flow-Through Sync SRAM Original PDF
    CY7C1298A Cypress Semiconductor Memory : Sync SRAMs Original PDF
    CY7C1298A-100NC Cypress Semiconductor 64K x 18 Synchronous Burst RAM Pipelined Output Original PDF
    CY7C1298A-83NC Cypress Semiconductor Memory : Sync SRAMs Original PDF
    CY7C1298F Cypress Semiconductor 1-Mb (64K x 18) Pipelined DCD Sync SRAM Original PDF
    CY7C1298F-133AC Cypress Semiconductor 1-Mb (64K x 18) Pipelined DCD Sync SRAM Original PDF
    CY7C1298H Cypress Semiconductor 1-Mbit (64K x 18) Pipelined DCD Sync SRAM Original PDF

    CY7C129 Datasheets Context Search

    Catalog Datasheet Type Document Tags PDF

    CY7C1298A

    Abstract: GVT7164C18
    Text: 298A CY7C1298A/ GVT7164C18 64K x 18 Synchronous Burst RAM Pipelined Output Features • • • • • • • • • • • • • • • • • • • The CY7C1298A/GVT7164C18 SRAM integrates 65536x18 SRAM cells with advanced synchronous peripheral circuitry


    Original     		CY7C1298A/ GVT7164C18 CY7C1298A/GVT7164C18 65536x18 CY7C1315A CY7C1298A CY7C1298A GVT7164C18 PDF

    CY7C1298H

    Abstract: CY7C1298H-100AXC
    Text: CY7C1298H 1-Mbit 64K x 18 Pipelined DCD Sync SRAM Functional Description[1] Features • Registered inputs and outputs for pipelined operation • Optimal for performance (Double-Cycle deselect) — Depth expansion without wait state • 64K x 18-bit common I/O architecture


    Original     		CY7C1298H 18-bit 166-MHz 100-Pin CY7C1298H CY7C1298H-100AXC PDF

    CY7C1292DV18

    Abstract: CY7C1294DV18
    Text: CY7C1292DV18 CY7C1294DV18 9-Mbit QDR- II SRAM 2-Word Burst Architecture Features Functional Description • Separate Independent Read and Write data ports The CY7C1292DV18 and CY7C1294DV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR™-II architecture. QDR-II architecture consists of two separate


    Original     		CY7C1292DV18 CY7C1294DV18 CY7C1292DV18 CY7C1294DV18 PDF

    Untitled

    Abstract: No abstract text available
    Text: CY7C1292DV18 CY7C1294DV18 PRELIMINARY 9-Mbit QDR-II SRAM 2-Word Burst Architecture Features Configurations • Separate Independent Read and Write data ports — Supports concurrent transactions • 300-MHz clock for high bandwidth • 2-Word Burst on all accesses


    Original     		CY7C1292DV18 CY7C1294DV18 300-MHz CY7C1292DV18/CY7C1294DV18 PDF

    CY7C1299A

    Abstract: No abstract text available
    Text: 299A CY7C1299A 32K X 36 Dual I/O Dual Address Synchronous SRAM Features • • • • • • • • • • • • • • • • Fast clock speed: 100 and 83 MHz Fast Access Times: 5.0/6.0 ns Max. Single Clock Operation Single 3.3V –5% and +5% power supply VCC


    Original     		CY7C1299A 176-Pin CY7C1299A PDF

    waveforms of single port asynchronous read and w

    Abstract: CY7C1299A
    Text: CY7C1299A 32K x 36 Dual I/O Dual Address Synchronous SRAM Features • • • • • • • • • • • • • • • • Fast clock speed: 100 and 83 MHz Fast access times: 5.0/6.0 ns max. Single clock operation Single 3.3V –5% and +5% power supply VCC


    Original     		CY7C1299A 176-pin CY7C1299A waveforms of single port asynchronous read and w PDF

    CY7C1292DV18

    Abstract: CY7C1294DV18
    Text: CY7C1292DV18 CY7C1294DV18 9-Mbit QDR- II SRAM 2-Word Burst Architecture Features Functional Description • Separate Independent Read and Write data ports The CY7C1292DV18 and CY7C1294DV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR™-II architecture. QDR-II architecture consists of two separate


    Original     		CY7C1292DV18 CY7C1294DV18 CY7C1292DV18 CY7C1294DV18 PDF

    CY7C1297H

    Abstract: CY7C1297H-100AXC
    Text: CY7C1297H 1-Mbit 64K x 18 Flow-Through Sync SRAM Functional Description[1] Features • 64K x 18 common I/O • 3.3V core power supply (VDD) • 2.5V/3.3V I/O power supply (VDDQ) • Fast clock-to-output times — 6.5 ns (for 133-MHz version) • Provide high-performance 2-1-1-1 access rate


    Original     		CY7C1297H 133-MHz 100-Pin CY7C1297H CY7C1297H-100AXC PDF

    Untitled

    Abstract: No abstract text available
    Text: CY7C1297H PRELIMINARY 1-Mbit 64K x 18 Flow-Through Sync SRAM Functional Description[1] Features • 64K x 18 common I/O • 3.3V –5% and +10% core power supply (VDD) • 3.3V I/O supply (VDDQ) • Fast clock-to-output times — 6.5 ns (133-MHz version)


    Original     		CY7C1297H 133-MHz 100-MHz 100-pin CY7C1297H PDF

    CY7C1297A

    Abstract: GVT7164B18
    Text: 297A CY7C1297A/ GVT7164B18 64K X 18 Synchronous Burst SRAM Features • • • • • • • • • • • • • • • • • Fast access times: 9 and 10 ns Fast clock speed: 66 and 50 MHz Provide high performance 2-1-1-1 access rate Fast OE access times: 5 and 6 ns


    Original     		CY7C1297A/ GVT7164B18 1-85050-A CY7C1297A/GVT7164B18 CY7C1314A CY7C1297A CY7C1297A GVT7164B18 PDF

    CY7C1297H

    Abstract: CY7C1297H-133AXC
    Text: CY7C1297H 1-Mbit 64K x 18 Flow-Through Sync SRAM Functional Description[1] Features • 64K x 18 common I/O • 3.3V core power supply (VDD) • 2.5V/3.3V I/O power supply (VDDQ) • Fast clock-to-output times — 6.5 ns (for 133-MHz version) • Provide high-performance 2-1-1-1 access rate


    Original     		CY7C1297H 133-MHz 100-Pin CY7C1297H CY7C1297H-133AXC PDF

    A101

    Abstract: CY7C1297F CY7C1297F-117AC
    Text: CY7C1297F 1-Mbit 64K x 18 Flow-Through Sync SRAM Features • 64K x 18 common I/O • 3.3V –5% and +10% core power supply (VDD) • 3.3V I/O supply (VDDQ) • Fast clock-to-output times — 6.5 ns (133-MHz version) — 7.5 ns (117-MHz version) • Provide high-performance 2-1-1-1 access rate


    Original     		CY7C1297F 133-MHz 117-MHz 100-pin CY7C1297F A101 CY7C1297F-117AC PDF

    BV25

    Abstract: CY7C129 CY7C130 CY7C131 CY7C132 EV25 ev18
    Text: CY7C129*DV18/CY7C130*DV25 CY7C130*BV18/CY7C130*BV25/CY7C132*BV25 CY7C131*BV18 / CY7C132*BV18/CY7C139*BV18 CY7C191*BV18/CY7C141*AV18 / CY7C142*AV18/ CY7C151*V18 /CY7C152*V18 Errata Revision: *D March 04, 2008 RAM9 QDR-I/DDR-I/QDR-II/DDR- II Errata This document describes the DOFF issue for QDRII/DDRII, the Output Buffer, the JTAG and the DLL issue for


    Original     		CY7C129 DV18/CY7C130 CY7C130 BV18/CY7C130 BV25/CY7C132 CY7C131 CY7C132 BV18/CY7C139 CY7C191 BV18/CY7C141 BV25 EV25 ev18 PDF

    CY7C1297H

    Abstract: CY7C1297H-100AXC
    Text: CY7C1297H 1-Mbit 64K x 18 Flow-Through Sync SRAM Functional Description[1] Features • 64K x 18 common I/O • 3.3V core power supply (VDD) • 2.5V/3.3V I/O power supply (VDDQ) • Fast clock-to-output times — 6.5 ns (for 133-MHz version) • Provide high-performance 2-1-1-1 access rate


    Original     		CY7C1297H 133-MHz 100-Pin CY7C1297H CY7C1297H-100AXC PDF

    Untitled

    Abstract: No abstract text available
    Text: CY7C1298F 1-Mb 64K x 18 Pipelined DCD Sync SRAM Functional Description[1] Features • Registered inputs and outputs for pipelined operation • Optimal for performance (Double-Cycle deselect) — Depth expansion without wait state • 64K x 18-bit common I/O architecture


    Original     		CY7C1298F 18-bit 166-MHz 133-MHz 100-pin CY7C1298F PDF

    112434

    Abstract: CY7C1297A GVT7164B18
    Text: 297A CY7C1297A/ GVT7164B18 64K X 18 Synchronous Burst SRAM Features • • • • • • • • • • • • • • • • • Fast access times: 9 and 10 ns Fast clock speed: 66 and 50 MHz Provide high performance 2-1-1-1 access rate Fast OE access times: 5 and 6 ns


    Original     		CY7C1297A/ GVT7164B18 CY7C1297A/GVT7164B18 CY7C1314A CY7C1297A 112434 CY7C1297A GVT7164B18 PDF

    A101

    Abstract: CY7C1298F CY7C1298F-133AC
    Text: CY7C1298F 1-Mbit 64K x 18 Pipelined DCD Sync SRAM Functional Description[1] Features • Registered inputs and outputs for pipelined operation • Optimal for performance (Double-Cycle deselect) — Depth expansion without wait state • 64K x 18-bit common I/O architecture


    Original     		CY7C1298F 18-bit 166-MHz 133-MHz 100-pin CY7C1298F A101 CY7C1298F-133AC PDF

    05564

    Abstract: BV25 CY7C129 CY7C130 CY7C131 CY7C132 CY7C1422AV18 1428A
    Text: CY7C129*DV18/CY7C130*DV25 CY7C130*BV18/CY7C130*BV25/CY7C132*BV25 CY7C131*BV18 / CY7C132*BV18/CY7C139*BV18 CY7C191*BV18/CY7C141*AV18 / CY7C142*AV18/ CY7C151*V18 /CY7C152*V18 Errata Revision: *C May 02, 2007 RAM9 QDR-I/DDR-I/QDR-II/DDR- II Errata This document describes the DOFF issue for QDRII/DDRII and the Output Buffer and JTAG issues for


    Original     		CY7C129 DV18/CY7C130 CY7C130 BV18/CY7C130 BV25/CY7C132 CY7C131 CY7C132 BV18/CY7C139 CY7C191 BV18/CY7C141 05564 BV25 CY7C1422AV18 1428A PDF

    Untitled

    Abstract: No abstract text available
    Text: CY7C1298H 1-Mbit 64K x 18 Pipelined DCD Sync SRAM Functional Description[1] Features • Registered inputs and outputs for pipelined operation • Optimal for performance (Double-Cycle deselect) — Depth expansion without wait state • 64K x 18-bit common I/O architecture


    Original     		CY7C1298H 18-bit 166-MHz 100-Pin PDF

    CY7C1299A

    Abstract: CE2Y 126-196
    Text: CY7C1299A 32K x 36 Dual I/O Dual Address Synchronous SRAM Features • • • • • • • • • • • • • • • • Fast clock speed: 100 and 83 MHz Fast access times: 5.0/6.0 ns max. Single clock operation Single 3.3V –5% and +5% power supply VCC


    Original     		CY7C1299A 176-pin CY7C1299A CE2Y 126-196 PDF

    Untitled

    Abstract: No abstract text available
    Text: THIS SPEC IS OBSOLETE Spec No: 001-00350 Spec Title: CY7C1292DV18/CY7C1294DV18 9-Mbit QDR II SRAM 2-Word Burst Architecture Sunset Owner: AJU Replaced By: None CY7C1292DV18 CY7C1294DV18 9-Mbit QDR® II SRAM 2-Word Burst Architecture Features Configurations


    Original     		CY7C1292DV18/CY7C1294DV18 CY7C1292DV18 CY7C1294DV18 PDF

    CY7C1298A

    Abstract: GVT7164C18
    Text: 298A CY7C1298A/ GVT7164C18 64K x 18 Synchronous Burst RAM Pipelined Output Features • • • • • • • • • • • • • • • • • • • The CY7C1298A/GVT7164C18 SRAM integrates 65536x18 SRAM cells with advanced synchronous peripheral circuitry


    Original     		CY7C1298A/ GVT7164C18 CY7C1298A/GVT7164C18 65536x18 CY7C1315A CY7C1298A CY7C1298A GVT7164C18 PDF

    A101

    Abstract: CY7C1298F CY7C1298F-133AC
    Text: CY7C1298F 1-Mbit 64K x 18 Pipelined DCD Sync SRAM Functional Description[1] Features • Registered inputs and outputs for pipelined operation • Optimal for performance (Double-Cycle deselect) — Depth expansion without wait state • 64K x 18-bit common I/O architecture


    Original     		CY7C1298F 18-bit 166-MHz 133-MHz 100-pin CY7C1298F A101 CY7C1298F-133AC PDF

    ay-13

    Abstract: CY7C1299A
    Text: CY7C1299A 32K x 36 Dual I/O Dual Address Synchronous SRAM Features • • • • • • • Fast clock speed: 100 and 83 MHz Fast access times: 5.0/6.0 ns max. Single clock operation Single 3.3V –5% and +5% power supply VCC Separate VCCQ for output buffer


    Original     		CY7C1299A 176-pin CY7C1299A ay-13 PDF