3M Touch Systems
Abstract: No abstract text available
Text: CY7C1646KV18, CY7C1657KV18 CY7C1648KV18, CY7C1650KV18 144-Mbit DDR II+ SRAM 2-Word Burst Architecture 2.0 Cycle Read Latency 144-Mbit DDR II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency) Features Configurations • 144-Mbit density (16 M x 8, 16 M × 9, 8 M × 18, 4 M × 36)
|
Original
|
CY7C1646KV18,
CY7C1657KV18
CY7C1648KV18,
CY7C1650KV18
144-Mbit
CY7C1646KV18
CY7C1657KV18
CY7C1648KV18
3M Touch Systems
|
PDF
|
Untitled
Abstract: No abstract text available
Text: CY7C1648KV18 CY7C1650KV18 144-Mbit DDR II+ SRAM Two-Word Burst Architecture 2.0 Cycle Read Latency 144-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency) Features • JTAG 1149.1 compatible test access port Phase locked loop (PLL) for accurate data placement
|
Original
|
CY7C1648KV18
CY7C1650KV18
144-Mbit
450-MHz
|
PDF
|
Untitled
Abstract: No abstract text available
Text: CY7C1648KV18 CY7C1650KV18 144-Mbit DDR II+ SRAM Two-Word Burst Architecture 2.0 Cycle Read Latency 144-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency) Features • JTAG 1149.1 compatible test access port ■ Phase locked loop (PLL) for accurate data placement
|
Original
|
CY7C1648KV18
CY7C1650KV18
144-Mbit
450-MHz
|
PDF
|
3M Touch Systems
Abstract: No abstract text available
Text: CY7C1648KV18 CY7C1650KV18 144-Mbit DDR II+ SRAM Two-Word Burst Architecture 2.0 Cycle Read Latency 144-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency) Features • JTAG 1149.1 compatible test access port ■ Phase locked loop (PLL) for accurate data placement
|
Original
|
CY7C1648KV18
CY7C1650KV18
144-Mbit
450-MHz
3M Touch Systems
|
PDF
|