Untitled
Abstract: No abstract text available
Text: Advance Data Sheet August 1998 LU5M31 Gigabit Ethernet Media Access Controller MAC Overview The LU5M31 is a single-port 1 Gbit/s MAC that incorporates physical coding sublayer (PCS) functionality. The LU5M31 is intended to enhance 10/ 100 Mbits/s Ethernet frame switching, multiple port
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LU5M31
LU5M31
8b/10b
DS98-351LAN
DS97-447LAN)
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ADSP-21000
Abstract: ADSP-21020 ADSP-21060 ADSP-21062 ADSP-21062L tddg
Text: a ADSP-2106x SHARC DSP Microcomputer Family ADSP-21062/ADSP-21062L SUMMARY High Performance Signal Processor for Communications, Graphics and Imaging Applications Super Harvard Architecture Four Independent Buses for Dual Data Fetch, Instruction Fetch and Nonintrusive I/O
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ADSP-2106x
ADSP-21062/ADSP-21062L
32-Bit
240-Lead
225-Ball
40-Bit
ADSP-21062KS-133
ADSP-21062KS-160
ADSP-21000
ADSP-21020
ADSP-21060
ADSP-21062
ADSP-21062L
tddg
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031MF
Abstract: No abstract text available
Text: PM73122 AAL1GATOR-32 PRELIMINARY STANDARD PRODUCT DATASHEET PMC-1981419 ISSUE 4 32 LINK CES/DBCES AAL1 SAR PM73122 AAL1GATOR-32 ATM ADAPTATION LAYER 1 SEGMENTATION AND REASSEMBLY PROCESSOR-32 DATASHEET PROPRIETARY AND CONFIDENTIAL PRELIMINARY ISSUE 4: JANUARY 2000
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PMC-1981419
PM73122
AAL1GATOR-32
PM73122
PROCESSOR-32
PMC-1981419
031MF
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ADVANCED COMMUNICATION DEVICES
Abstract: ACD80800 ACD80900 ACD82216 ACD82224 16N03 P03R
Text: Advanced Communication Devices Corp ADVANCE INFORMATION Data Sheet: ACD82224 ACD82224 24 Ports 10/100 Fast Ethernet Switch Last Update: September 19, 2000 Please check ACD’ s website for update information before starting a design Web site: http://www.acdcorp.com
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ACD82224
Register-20
ADVANCED COMMUNICATION DEVICES
ACD80800
ACD80900
ACD82216
ACD82224
16N03
P03R
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SMD45
Abstract: SMD34 224 d5 smd zd 15 p240f1 SMD52 SMD46 SMD-42 smd M16 SMD23
Text: お客様各位 カタログ等資料中の旧社名の扱いについて 2010 年 4 月 1 日を以って NEC エレクトロニクス株式会社及び株式会社ルネサステクノロジ が合併し両社の全ての事業が当社に承継されております。従いまして、本資料中には旧社
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PD98421
PD98421
MHz50
S13650JJ6V0DS
P240F1-80-GA5
SMD45
SMD34
224 d5
smd zd 15
p240f1
SMD52
SMD46
SMD-42
smd M16
SMD23
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AT17256
Abstract: 7Pin din Connector AN076 qfp 32 k2511 phillips handbook XPLA1 UNSIGNED SERIAL DIVIDER using vhdl
Text: APPLICATION NOTE AN076 Using the Philips PZ3960 Evaluation Board 1998 Jul 21 Philips Semiconductors Application note Using the Philips PZ3960 Evaluation Board AN076 INTRODUCTION This note discusses the use of the Philips PZ3960 evaluation board. The main functions of the evauation board are the
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AN076
PZ3960
PZ3960
PZ3128
PZ3128.
AT17256
7Pin din Connector
AN076
qfp 32
k2511
phillips handbook
XPLA1
UNSIGNED SERIAL DIVIDER using vhdl
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Untitled
Abstract: No abstract text available
Text: To our customers, Old Company Name in Catalogs and Other Documents On April 1st, 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the old company name remains in this document, it is a valid
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Untitled
Abstract: No abstract text available
Text: a Commercial Grade SHARC Family DSP Microcomputer ADSP-21061/ADSP-21061L SUMMARY High performance signal processor for communications, graphics, and imaging applications Super Harvard Architecture Four independent buses for dual data fetch, instruction fetch, and nonintrusive I/O
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ADSP-21061/ADSP-21061L
32-bit
240-Lead
225-Ball
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SMD phase shifter 0201
Abstract: ts201S ADSP-TS201SABP-050 ADSP-TS201SABP-060 l3bc
Text: TigerSHARC Embedded Processor ADSP-TS201S • a KEY FEATURES KEY BENEFITS Up to 600 MHz, 1.67 ns instruction cycle rate 24M bits of internal—on-chip—DRAM memory 25 mm x 25 mm 576-ball thermally enhanced ball grid array package Dual-computation blocks—each containing an ALU, a
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576-ball)
14-channel
32-bit
40-bit
64-bit
BP-576
576-Ball
SMD phase shifter 0201
ts201S
ADSP-TS201SABP-050
ADSP-TS201SABP-060
l3bc
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Supersparc
Abstract: IEEE754 STP1021A
Text: STP1021A July 1997 SuperSPARC -II DATA SHEET SPARC v8 32-Bit Superscalar Microprocessor DESCRIPTION The STP1021A is a new member of the SuperSPARC-II family of microprocessor products. Like its predecessors STP1020N, STP1020 and STP1021 this new part is fully SPARC Version 8 compliant and is completely upward compatible with the earlier SPARC Version 7 implementations running over 9,400 SPARC applications and development
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STP1021A
32-Bit
STP1021A
STP1020N,
STP1020
STP1021)
instructionta32
addr18
data50
Supersparc
IEEE754
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ADSP-21000
Abstract: ADSP-21020 ADSP-21060 ADSP21061 ADSP-21061 ADSP21061L ADSP-21061L ADSP-21062 ADSP 21 XXX Sharc processor
Text: September 1997 ADSP-21061L SHARC Preliminary Data Sheet For current information contact Analog Devices at 617 461-3881 ADSP-21061L SHARC Preliminary Data Sheet SUMMARY • High-Performance Signal Computer for Speech, Audio, Graphics, Control, and Imaging Applications
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ADSP-21061L
32-Bit
ADSP-21061LKS-133x
ADSP-21061LKS-160x
P3200-2
ADSP-21000
ADSP-21020
ADSP-21060
ADSP21061
ADSP-21061
ADSP21061L
ADSP-21062
ADSP 21 XXX Sharc processor
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mpc560xb bolero
Abstract: MPC5606B CHN 949 transistor BC 247 LINFlex PROTOCOL linflex MPC560xB "Base Station subsystem 30f131 pj 989
Text: Devices Supported: MPC5607B MPC5607BRM Rev. 5 31 Jan 2010 MPC5607B Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor Preliminary—Subject to Change Without Notice 1 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available
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MPC5607B
MPC560xB
MPC5607BRM
MPC5607B
mpc560xb bolero
MPC5606B
CHN 949
transistor BC 247
LINFlex PROTOCOL
linflex
"Base Station subsystem
30f131
pj 989
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IC 651
Abstract: contactless Functional Specification EN753-2 nxp proximity antenna design 7816-6 AMD1 NXP antenna design guide
Text: MF0 IC U1 Functional specification contactless single-trip ticket IC Rev. 3.2 — 3 April 2007 Product data sheet 028632 PUBLIC 1. General description NXP has developed the mifare MF0 IC U1 to be used with Proximity Coupling Devices PCD according to ISO/IEC14443A. The communication layer (mifare RF Interface)
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ISO/IEC14443A.
ISO/IEC14443A
EN753-2.
IC 651
contactless Functional Specification
EN753-2
nxp proximity antenna design
7816-6 AMD1
NXP antenna design guide
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TDSR 5130
Abstract: TDSR 5130 H TDSR 5130 g TDSR SQFP208 SAA6750H SAA7111 SAA7146 iso 13818-2 SAA711x
Text: INTEGRATED CIRCUITS DATA SHEET SAA6750H Encoder for MPEG2 image recording EMPIRE Preliminary specification File under Integrated Circuits, IC02 1998 Sep 07 Philips Semiconductors Preliminary specification Encoder for MPEG2 image recording (EMPIRE) SAA6750H
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SAA6750H
SCA60
545104/750/01/pp64
TDSR 5130
TDSR 5130 H
TDSR 5130 g
TDSR
SQFP208
SAA6750H
SAA7111
SAA7146
iso 13818-2
SAA711x
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adsp 210xx architecture diagram
Abstract: ADSP-21000 ADSP-21060 ADSP-21061 ADSP-21061L ADSP-21062 ADDS-2106x-EZ-Lite
Text: a ADSP-2106x SHARC DSP Microcomputer Family ADSP-21061/ADSP-21061L Pin-Compatible with ADSP-21060 4 Mbit and ADSP-21062 (2 Mbit) Flexible Data Formats and 40-Bit Extended Precision 32-Bit Single-Precision and 40-Bit Extended-Precision IEEE Floating-Point Data Formats
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ADSP-2106x
ADSP-21061/ADSP-21061L
ADSP-21060
ADSP-21062
40-Bit
32-Bit
80-Bit
adsp 210xx architecture diagram
ADSP-21000
ADSP-21060
ADSP-21061
ADSP-21061L
ADSP-21062
ADDS-2106x-EZ-Lite
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EE-68
Abstract: ts201 Embedded Processor Preliminary Data Sheet link port ts201 32X32 ADSP-TS201S l3bc ADSP-TS201SABP-6X ADSP-TS201SABP-X
Text: TigerSHARC Embedded Processor ADSP-TS201S Preliminary Technical Data KEY FEATURES KEY BENEFITS Up to 600 MHz, 1.67 ns Instruction Cycle Rate 24M Bits of Internal—On-Chip—DRAM Memory 25x25 mm 576-Ball Thermally Enhanced Ball Grid Array Package Dual Computation Blocks—Each Containing an ALU, a Multiplier, a Shifter, a Register File, and a Communications Logic
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ADSP-TS201S
576-Ball)
24Mbit
BP-576
ADSP-TS201SABP-X
C00000-0-03/03
BP-576)
EE-68
ts201 Embedded Processor Preliminary Data Sheet
link port ts201
32X32
ADSP-TS201S
l3bc
ADSP-TS201SABP-6X
ADSP-TS201SABP-X
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PCR 406 J
Abstract: MPC5605 MPC5606B MPC5605B PCR 606 J MPC5607BRM transistor pcr 606 j MPC5607B APC UPS CIRCUIT DIAGRAM 7M 0880 IC pin ,j10
Text: MPC5607B Microcontroller Reference Manual Devices Supported: MPC5607B MPC5606B MPC5605B MPC5607BRM Rev. 6 30 Jun 2010 MPC5607B Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 1 Preliminary—Subject to Change Without Notice Chapter 1 Overview
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MPC5607B
MPC5607B
MPC5606B
MPC5605B
MPC5607BRM
PCR 406 J
MPC5605
MPC5606B
MPC5605B
PCR 606 J
MPC5607BRM
transistor pcr 606 j
APC UPS CIRCUIT DIAGRAM
7M 0880 IC pin ,j10
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AD14060
Abstract: ad14060lbf AD14060L ADSP-21060 lA1d ms2107 ADSP-20160 22760a
Text: Quad-SHARC DSP Multiprocessor Family AD14060/AD14060L CS TIMEXP LINK 1 LINK 3 LINK 4 IRQ2–0 FLAG2, 0 CPA SPORT 1 SPORT 0 TCK, TMS, TRST FLAG1 FLAG3 TDO LINK 0 LINK 2 LINK 5 TDI SHARC_B EBOOT, LBOOT, BMS EMU CLKIN RESET SPORT 0 TCK, TMS, TRST FLAG1 FLAG3
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AD14060/AD14060L
ADDR31
DATA47
308-Lead
QS-308)
AD14060BF-4
AD14060LBF-4
C00667
AD14060
ad14060lbf
AD14060L
ADSP-21060
lA1d
ms2107
ADSP-20160
22760a
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in138
Abstract: SPARC v9 architecture BLOCK DIAGRAM cpu lga UltraSPARC ii
Text: S un M icro electro nics July 1997 UltraSPARC -!! CPU Module DATA SHEET Complete 296 MHz CPU, 2.0 MB E-Cache, UDB-II D e s c r ip t io n The UltraSPARC-II module is a high performance, SPARC V9 compliant, small form factor processor module. It interfaces to the UltraSPARC Port Architecture UPA interconnect bus.
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MC100LVE210
STP5212UPA-300
296MHz
100MHz
STP1031)
STP1081)
in138
SPARC v9 architecture BLOCK DIAGRAM
cpu lga
UltraSPARC ii
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SuperSPARC
Abstract: Mbus master 250 slave circuit tmx390 STP1091-60
Text: S un M icroelectronics July 1997 Multi-Cache Controller DATA SHEET Integrated Cache Controller for SuperSPARC D e s c r ip t io n The STP1091 is a high-performance external cache controller for the STP1020 SuperSPARC and STP1021 (SuperSPARC-II) microprocessors. It is used when a large secondary cache or an interface to a non-MBus sys
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STP1091
STP1020
STP1021
33x8k
STP1091PGA-75
STP1091PGA-90
STP1020HS
STP1091
SuperSPARC
Mbus master 250 slave circuit
tmx390
STP1091-60
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Untitled
Abstract: No abstract text available
Text: LS125 Data Sheet I-Cube SATC Controller Description Features 33 M Hz 32-bit PCI bus interface, 8 interrapt lines to support up to 8 LS port controllers. 32 or 48 bit Interface with standard asynchronous SRAM to internal port map registers cache up to 128K MAC addresses.
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LS125
32-bit
125-DS
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Untitled
Abstract: No abstract text available
Text: ADSP-2106x SHARC DSP Microcomputer Family ADSP-21062/ADSP-21060 ANALOG DEVICES SUMMARY High Performance Signal Processor for Communica tions, Graphics, and Imaging Applications Super Harvard ARchitecture Computer SHARC — Four Independent Buses for Dual Data Fetch,
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ADSP-2106x
ADSP-21062/ADSP-21060
32-Bit
ADSP-21060KS-133*
ADSP-21060KS-160*
ADSP-21060LKS-133*
ADSP-21060LKS-160*
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Untitled
Abstract: No abstract text available
Text: ADSP-2106X SHARC DSP Microcomputer Family ANALOG DEVICES ADSP-21061/ADSP-21061L S UM M AR Y High Performance Signal Com puter for Speech, Sound, Graphics and Imaging Applications Super Harvard Architecture Com puter SHARC — Four Independent Buses for Dual Data, Instructions,
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ADSP-2106X
ADSP-21061/ADSP-21061L
32-Bit
SP-21061
240-lead
-21061L
225-Ball
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csc 9803
Abstract: QML-38534 LA4-DA BMS SYSTEM qualification CE7Y
Text: REVISIONS LTR A DESCRIPTION DATE YR-MO-DA Add device type REV APPROVED 98-12-10_ K. A. Cottonqim A A A A A A A A A A A A A A A A A A A 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 REV A
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AD14060LBF/QML-4
5962-9750702HXC
AD14060LTF/QML-4
csc 9803
QML-38534
LA4-DA
BMS SYSTEM qualification
CE7Y
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