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    DDR2 SSTL_18 CLASS I Search Results

    DDR2 SSTL_18 CLASS I Result Highlights (5)

    Part ECAD Model Manufacturer Description Download Buy
    JA4575-BL Coilcraft Inc Dual inductor, for Class D, RoHS Visit Coilcraft Inc
    GA3416- Coilcraft Inc Dual inductor, for Class D, SMT, RoHS Visit Coilcraft Inc
    GA3416-CL Coilcraft Inc Dual inductor, for Class D, SMT, RoHS Visit Coilcraft Inc
    UA8014- Coilcraft Inc Dual inductor, for Class D, SMT, RoHS Visit Coilcraft Inc
    UA8013- Coilcraft Inc Dual inductor, for Class D, SMT, RoHS Visit Coilcraft Inc

    DDR2 SSTL_18 CLASS I Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    DDR2 SSTL class

    Abstract: SSTL_18 DDR1-400 DDR2 SDRAM with SSTL_18 interface TVSOP-48 SSTL-18 PCK2059 SSTV16857 DDR200 hp SSTU32866
    Text: Memory interfaces Support logic for memory modules and other memory subsystems Portfolio overview PC100 to PC133 • AVC, ALVC, AVCM, and ALVCH series registered drivers • PCK2509 and PCK2510 series PLL clock buffers DDR200 to DDR266 • SSTV and SSTL series registered drivers


    Original     		PDF PC100 PC133 PCK2509 PCK2510 DDR200 DDR266 DDR333 DDR400 PCKVF857 DDR2-400 DDR2 SSTL class SSTL_18 DDR1-400 DDR2 SDRAM with SSTL_18 interface TVSOP-48 SSTL-18 PCK2059 SSTV16857 hp SSTU32866

    A115-A

    Abstract: C101 SN74SSTU32864D SN74SSTU32864DGKER TOP-SIDE MARKING H2 SU864D
    Text: SN74SSTU32864D 25-BIT CONFIGURABLE REGISTERED BUFFER WITH SSTL_18 INPUTS AND OUTPUTS www.ti.com SCES623A – FEBRUARY 2005 – REVISED APRIL 2005 FEATURES • • • • • • Member of the Texas Instruments Widebus+ Family Pinout Optimizes DDR2 DIMM PCB Layout


    Original     		PDF SN74SSTU32864D 25-BIT SCES623A 14-Bit A115-A C101 SN74SSTU32864D SN74SSTU32864DGKER TOP-SIDE MARKING H2 SU864D

    Untitled

    Abstract: No abstract text available
    Text: SN74SSTU32864D 25-BIT CONFIGURABLE REGISTERED BUFFER WITH SSTL_18 INPUTS AND OUTPUTS www.ti.com SCES623A – FEBRUARY 2005 – REVISED APRIL 2005 FEATURES • • • • • • Member of the Texas Instruments Widebus+ Family Pinout Optimizes DDR2 DIMM PCB Layout


    Original     		PDF SN74SSTU32864D 25-BIT SCES623A 14-Bit

    DDR2 sdram pcb layout guidelines

    Abstract: DDR2 SDRAM with SSTL_18 interface SSTL18
    Text: SN74SSTU32864E 25-BIT CONFIGURABLE REGISTERED BUFFER WITH SSTL_18 INPUTS AND OUTPUTS www.ti.com SCAS802 – JULY 2005 FEATURES • • • • • • Member of the Texas Instruments Widebus+ Family Pinout Optimizes DDR2 DIMM PCB Layout Configurable as 25-Bit 1:1 or 14-Bit 1:2


    Original     		PDF SN74SSTU32864E 25-BIT SCAS802 14-Bit DDR2 sdram pcb layout guidelines DDR2 SDRAM with SSTL_18 interface SSTL18

    A115-A

    Abstract: C101 SN74SSTU32864C SN74SSTU32864CGKER
    Text: SN74SSTU32864C 25-BIT CONFIGURABLE REGISTERED BUFFER WITH SSTL_18 INPUTS AND OUTPUTS www.ti.com SCES542A – JANUARY 2004 – REVISED FEBRUARY 2005 FEATURES • • • • • • Member of the Texas Instruments Widebus+ Family Pinout Optimizes DDR2 DIMM PCB Layout


    Original     		PDF SN74SSTU32864C 25-BIT SCES542A 14-Bit A115-A C101 SN74SSTU32864C SN74SSTU32864CGKER

    Untitled

    Abstract: No abstract text available
    Text: SN74SSTU32864C 25-BIT CONFIGURABLE REGISTERED BUFFER WITH SSTL_18 INPUTS AND OUTPUTS www.ti.com SCES542B – JANUARY 2004 – REVISED APRIL 2005 FEATURES • • • • • • Member of the Texas Instruments Widebus+ Family Pinout Optimizes DDR2 DIMM PCB Layout


    Original     		PDF SN74SSTU32864C 25-BIT SCES542B 14-Bit

    Untitled

    Abstract: No abstract text available
    Text: SN74SSTU32864C 25-BIT CONFIGURABLE REGISTERED BUFFER WITH SSTL_18 INPUTS AND OUTPUTS www.ti.com SCES542B – JANUARY 2004 – REVISED APRIL 2005 FEATURES • • • • • • Member of the Texas Instruments Widebus+ Family Pinout Optimizes DDR2 DIMM PCB Layout


    Original     		PDF SN74SSTU32864C 25-BIT SCES542B 14-Bit

    Untitled

    Abstract: No abstract text available
    Text: SN74SSTU32864C 25-BIT CONFIGURABLE REGISTERED BUFFER WITH SSTL_18 INPUTS AND OUTPUTS www.ti.com SCES542B – JANUARY 2004 – REVISED APRIL 2005 FEATURES • • • • • • Member of the Texas Instruments Widebus+ Family Pinout Optimizes DDR2 DIMM PCB Layout


    Original     		PDF SN74SSTU32864C 25-BIT SCES542B 14-Bit

    Untitled

    Abstract: No abstract text available
    Text: SN74SSTU32864D 25-BIT CONFIGURABLE REGISTERED BUFFER WITH SSTL_18 INPUTS AND OUTPUTS www.ti.com SCES623A – FEBRUARY 2005 – REVISED APRIL 2005 FEATURES • • • • • • Member of the Texas Instruments Widebus+ Family Pinout Optimizes DDR2 DIMM PCB Layout


    Original     		PDF SN74SSTU32864D 25-BIT SCES623A 14-Bit

    Untitled

    Abstract: No abstract text available
    Text: SN74SSTU32864C 25-BIT CONFIGURABLE REGISTERED BUFFER WITH SSTL_18 INPUTS AND OUTPUTS www.ti.com SCES542B – JANUARY 2004 – REVISED APRIL 2005 FEATURES • • • • • • Member of the Texas Instruments Widebus+ Family Pinout Optimizes DDR2 DIMM PCB Layout


    Original     		PDF SN74SSTU32864C 25-BIT SCES542B 14-Bit

    A115-A

    Abstract: C101 SN74SSTU32864C SN74SSTU32864CGKER
    Text: SN74SSTU32864C 25-BIT CONFIGURABLE REGISTERED BUFFER WITH SSTL_18 INPUTS AND OUTPUTS www.ti.com SCES542B – JANUARY 2004 – REVISED APRIL 2005 FEATURES • • • • • • Member of the Texas Instruments Widebus+ Family Pinout Optimizes DDR2 DIMM PCB Layout


    Original     		PDF SN74SSTU32864C 25-BIT SCES542B 14-Bit A115-A C101 SN74SSTU32864C SN74SSTU32864CGKER

    Q11A

    Abstract: Q13A SSTU32864 SSTU32864EC
    Text: SSTU32864 1.8 V configurable registered buffer for DDR2 RDIMM applications Rev. 01 — 12 July 2004 Objective data 1. Description The SSTU32864 is a 25-bit 1:1 or 14-bit 1:2 configurable registered buffer designed for 1.7 V to 1.9 V VDD operation. All clock and data inputs are compatible with the JEDEC standard to SSTL_18. The


    Original     		PDF SSTU32864 SSTU32864 25-bit 14-bit Q11A Q13A SSTU32864EC

    LTI-SASF546-P26-X1

    Abstract: schematic diagram of laptop motherboard lv7745d lv7745dev LTI-SASF546 S29GL512N datasheet SFP LVDS altera samtec asp connector pcie X1 edge connector samtec ASP
    Text: Arria GX Development Board Reference Manual 101 Innovation Drive San Jose, CA 95134 www.altera.com Document Date: October 2007 Copyright 2007 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and


    Original     		PDF LPM95235 190mA 100-mil LTI-SASF546-P26-X1 schematic diagram of laptop motherboard lv7745d lv7745dev LTI-SASF546 S29GL512N datasheet SFP LVDS altera samtec asp connector pcie X1 edge connector samtec ASP

    MT9HTF12872RHI

    Abstract: reliability report ddr2 1GB
    Text: 1GB x72, SR 200-Pin DDR2 SDRAM SORDIMM Features DDR2 SDRAM SORDIMM MT9HTF12872RHZ – 1GB Features Figure 1: 200-Pin SORDIMM (R/C A) • 200-pin, small-outline registered dual in-line memory module • Fast data transfer rates: PC2-4200, PC2-5300, or PC2-6400


    Original     		PDF 200-Pin MT9HTF12872RHZ 200-pin, PC2-4200, PC2-5300, PC2-6400 18-compatible) 8192-cycle 09005aef83ebee86 htf9c128x72rhz MT9HTF12872RHI reliability report ddr2 1GB

    Untitled

    Abstract: No abstract text available
    Text: iPEM 4.2 Gb SDRAM-DDR2 AS4DDR264M64PBG1 64Mx64 DDR2 SDRAM w/ SHARED CONTROL BUS iNTEGRATED Plastic Encapsulated Microcircuit FEATURES BENEFITS DDR2 Data rate = 667, 533, 400 Available in Industrial, Enhanced and Military Temp Package: • Proprietary Enchanced Die Stacked iPEM


    Original     		PDF AS4DDR264M64PBG1 64Mx64 AS4DDR264M64PBG1

    H11M1

    Abstract: No abstract text available
    Text: i PEM 4.8 G b SDRAM-DDR2 Gb Austin Semiconductor, Inc. AS4DDR264M72PBG1 64Mx72 DDR2 SDRAM w/ SHARED CONTROL BUS iNTEGRATED Plastic Encapsulated Microcircuit FEATURES „ „ „ BENEFITS „ „ DDR2 Data rate = 667, 533, 400 Available in Industrial, Enhanced and Extended Temp


    Original     		PDF AS4DDR264M72PBG1 64Mx72 daDDR264M72PBG1 H11M1

    Untitled

    Abstract: No abstract text available
    Text: i PEM 4.8 G b SDRAM-DDR2 Gb Austin Semiconductor, Inc. AS4DDR264M72PBG1 64Mx72 DDR2 SDRAM w/ SHARED CONTROL BUS iNTEGRATED Plastic Encapsulated Microcircuit BENEFITS FEATURES „ „ „ „ „ „ „ „ „ „ „ „ „ „ „ „ „ „ „ „ „ „ DDR2 Data rate = 667, 533, 400


    Original     		PDF AS4DDR264M72PBG1 64Mx72 AS4DDR264M72PBG1

    Untitled

    Abstract: No abstract text available
    Text: i PEM 4.2 G b SDRAM-DDR2 Gb Austin Semiconductor, Inc. AS4DDR264M65PBG1 64Mx64 DDR2 SDRAM w/ DUAL CONTROL BUS iNTEGRATED Plastic Encapsulated Microcircuit BENEFITS FEATURES „ „ „ „ „ „ „ DDR2 Data rate = 667, 533, 400 Available in Industrial, Enhanced and Extended Temp


    Original     		PDF AS4DDR264M65PBG1 64Mx64 AS4DDR264M65PBG1

    H11M1

    Abstract: No abstract text available
    Text: i PEM 4.2 G b SDRAM-DDR2 Gb Austin Semiconductor, Inc. AS4DDR264M64PBG1 64Mx64 DDR2 SDRAM w/ SHARED CONTROL BUS iNTEGRATED Plastic Encapsulated Microcircuit BENEFITS FEATURES „ „ „ „ „ „ „ DDR2 Data rate = 667, 533, 400 Available in Industrial, Enhanced and Extended Temp


    Original     		PDF AS4DDR264M64PBG1 64Mx64 AS4DDR264M64PBG1 H11M1

    Untitled

    Abstract: No abstract text available
    Text: i PEM 4.8 G b SDRAM-DDR2 Gb Austin Semiconductor, Inc. AS4DDR264M72PBG1 64Mx72 DDR2 SDRAM w/ SHARED CONTROL BUS iNTEGRATED Plastic Encapsulated Microcircuit FEATURES „ „ „ BENEFITS „ „ DDR2 Data rate = 667, 533, 400 Available in Industrial, Enhanced and Military Temp


    Original     		PDF AS4DDR264M72PBG1 64Mx72

    RAS 2415

    Abstract: No abstract text available
    Text: i PEM 4.8 G b SDRAM-DDR2 Gb Austin Semiconductor, Inc. AS4DDR264M72PBG1 64Mx72 DDR2 SDRAM w/ SHARED CONTROL BUS iNTEGRATED Plastic Encapsulated Microcircuit BENEFITS FEATURES „ „ „ „ „ „ „ „ „ „ „ „ „ „ „ „ „ „ „ „ „ „ DDR2 Data rate = 667, 533, 400


    Original     		PDF AS4DDR264M72PBG1 64Mx72 AS4DDR264M72PBG1 RAS 2415

    Untitled

    Abstract: No abstract text available
    Text: 64Mx72 bits DDR2 SDRAM Registered DIMM HYMP564R72A L 8 DESCRIPTION Preliminary Hynix HYMP564R72(L)8 series is registered 240-pin double data rate 2 Synchronous DRAM Dual In-Line Memory Modules(DIMMs) which are organized as 64Mx72 high-speed memory arrays. Hynix HYMP564R72(L)8 series consists of nine 64Mx8 DDR2 SDRAMs in 60-Lead FBGA chipsize packages. Hynix HYMP564R72(L)8 series provide a


    Original     		PDF 64Mx72 HYMP564R72A HYMP564R72 240-pin 64Mx8 60-Lead

    Untitled

    Abstract: No abstract text available
    Text: i PEM 4.8 G b SDRAM-DDR2 Gb Austin Semiconductor, Inc. AS4DDR264M72PBG1 64Mx72 DDR2 SDRAM w/ SHARED CONTROL BUS iNTEGRATED Plastic Encapsulated Microcircuit FEATURES „ „ „ BENEFITS „ „ DDR2 Data rate = 667, 533, 400 Available in Industrial, Enhanced and Extended Temp


    Original     		PDF AS4DDR264M72PBG1 64Mx72 AS4DDR264M72PBG1

    DQ72

    Abstract: No abstract text available
    Text: iPEM 4.8 Gb SDRAM-DDR2 AS4DDR264M72PBG & MYXDDR264M72 64Mx72 DDR2 SDRAM iNTEGRATED Plastic Encapsulated Microcircuit FEATURES                   BENEFITS DDR2 Data rate = 667, 533, 400 Available in Industrial, Enhanced and Military Temp


    Original     		PDF AS4DDR264M72PBG MYXDDR264M72 64Mx72 MYXDDR264M72 DQ72