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    FOR IC 74LS11 Search Results

    FOR IC 74LS11 Result Highlights (5)

    Part ECAD Model Manufacturer Description Download Buy
    74HC4053FT Toshiba Electronic Devices & Storage Corporation CMOS Logic IC, SPDT(1:2)/Analog Multiplexer, TSSOP16B, -40 to 125 degC Visit Toshiba Electronic Devices & Storage Corporation
    7UL2T125FK Toshiba Electronic Devices & Storage Corporation One-Gate Logic(L-MOS), Buffer, SOT-765 (US8), -40 to 85 degC Visit Toshiba Electronic Devices & Storage Corporation
    7UL2T126FK Toshiba Electronic Devices & Storage Corporation One-Gate Logic(L-MOS), Buffer, SOT-765 (US8), -40 to 85 degC Visit Toshiba Electronic Devices & Storage Corporation
    74HC4051FT Toshiba Electronic Devices & Storage Corporation CMOS Logic IC, SP8T(1:8)/Analog Multiplexer, TSSOP16B, -40 to 125 degC Visit Toshiba Electronic Devices & Storage Corporation
    7UL1G07FU Toshiba Electronic Devices & Storage Corporation One-Gate Logic(L-MOS), Non-Inverter Buffer (Open Drain), USV, -40 to 85 degC Visit Toshiba Electronic Devices & Storage Corporation
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    FOR IC 74LS11 Price and Stock

    Semiconductors 74LS11

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    Onlinecomponents.com 74LS11 7,351
    • 1 $3.82
    • 10 $3.82
    • 100 $1.37
    • 1000 $0.41
    • 10000 $0.41
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    FOR IC 74LS11 Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    74S113PC

    Abstract: 54S113DM
    Text: 1 NATIONAL SEfHCOND -CLOGIO DEE D I tiSGllSE DGbBTfii T T ~ *f¿ - 0 7 -0 7 Fl3 CO N N ECTIO N DIAGRAM PINO UT A 54S /74S 113 54LS /74LS113 D UA L JK E D G E -T R IG G E R E D FLIP-FLOP D ESC R IP TIO N — T h e '1 13offers individual J , K, Set and Clock inputs. When


    OCR Scan     		PDF /74LS113 13offers S/74LS 54/74S 54/74LS fl-07 74S113PC 54S113DM

    so 54 t

    Abstract: 74ls 3-input and gate TTL IC 74 SN74LS 74LS11 Motorola 74LS TTL 74LS11 74ls11 ic for IC 74LS11 all gate ic data 74
    Text: M MOTOROLA SN54/74LS11 TRIPLE 3-INPUT AND GATE TRIPLE 3-INPUT AND GATE v cc un r¡7j rrii rm nói m LOW POWER SCHOTTKY rn =§y n J SUFFIX C E R A M IC C A SE 632-08 14 GND 1 N SUFFIX PLA S TIC C A SE 646-06 D SUFFIX 14 1 SO IC C A S E 751A-02 5 ORDERING INFORMATION


    OCR Scan     		PDF SN54/74LS11 51A-02 SN54/74LS so 54 t 74ls 3-input and gate TTL IC 74 SN74LS 74LS11 Motorola 74LS TTL 74LS11 74ls11 ic for IC 74LS11 all gate ic data 74

    74LS11 pin configuration

    Abstract: PIN CONFIGURATION 7411 74ls characteristics 7411 pin configuration N7411F N7411N N74H11F N74H11N N74LS11F N74LS11N
    Text: 54/7411 54H/74H11 54S/74S11 54LS/74LS11 ORDERING CODE PIN CONFIGURATION See Section 9 for further Package and Ordering Information. C O M M E R C IA L RANGES ± 5%; Ta - 0°C to *70°C PACKAGES PIN CO N F. VCC = 5V P lastic DIP Fig. A Fig. A N 741 1 N N74S11N


    OCR Scan     		PDF 54H/74H11 54S/74S11 54LS/74LS11 N7411N N74H11N N74S11N N74LS11N N7411F N74H11F N74S11F 74LS11 pin configuration PIN CONFIGURATION 7411 74ls characteristics 7411 pin configuration N7411F N7411N N74LS11F N74LS11N

    74LS412

    Abstract: 74LS41 74ls112n 74LS112D 74ls112 pin configuration 74LS112
    Text: 74LS112, S112 Signetics Flip-Flops Dual J-K Edge-Triggered Flip-Flop Product Specification Logic Products DESCRIPTION The '112 is a dual J-K negative edgetriggered flip-flop featuring individual J, K, Clock, Set and Reset inputs. The Set So and Reset (R q) inputs, when LOW,


    OCR Scan     		PDF 74LS112, 500ns 500ns 74LS412 74LS41 74ls112n 74LS112D 74ls112 pin configuration 74LS112

    74LS112A

    Abstract: No abstract text available
    Text: M JW 0 T 0 f3 0 1 .X SN54/74LS112A D E S C R I P T I O N — The S N 5 4 L S /7 4 L S 1 1 2 A d u a l J K flip-flop features individual J, K, clock, and asynchronous set and clear inputs to each flip-flop. W h en the c lock goes HIGH, the inputs are enabled and data


    OCR Scan     		PDF SN54/74LS112A 74LS112A

    74LS114

    Abstract: 74ls114d 74S114DC
    Text: 114 C O N N E C T IO N D IA G R A M PINOUT A •01 ! .54S/74S114 54LS/74LS114 D I / ö H p 003 DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP c5{T 1 4 ] Vcc k , T (With Common Clocks and Clears K, C P J i CO S pi Qi Qi Ji[ T n ] cp m D E S C R IP T IO N — The '114 features individual J, K and set inputs and com­


    OCR Scan     		PDF 54S/74S114 54LS/74LS114 54/74LS 54/74S 54/74L 74LS114 74ls114d 74S114DC

    ic 7411

    Abstract: ic 7411 g 7411 ic 74LS11D 74LS11
    Text: I bSQliaB NATIONAL SENICOND {LOGIC} G2E D DQt>3b4ö 2 I r^ - / r TI C O N N E C T IO N D IA G R A M S PIN O U T A 54/7411 54H/74H11 54S/74S11 54LS/74LS11 T R IP L E 3-IN PU T A N D G A T E O R D E R IN G C O D E: See Section 9 C O M M E R C IA L G R A D E


    OCR Scan     		PDF 54H/74H11 54S/74S11 54LS/74LS11 74H11PC 74S11PC, 4LS11 74H11DC 74S11DC, 74LS11D 74S11FC, ic 7411 ic 7411 g 7411 ic 74LS11

    74LS114

    Abstract: cpj2 8 pin dip j k flipflop ic
    Text: ' NATIONAL SENICOND -CLOCICJ OSE D | b SO llS S 00^37^1 7 | 114 ~ F m -0 7 -0 7 CO NNECTIO N DIAGRAM PINOUT A 54S/74S114 54LS/74LS114 DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP c 5 [T ETL Ki T (With Common Clocks and Clears K i CP J t CO Sd ) Qi Ji [ T Oi


    OCR Scan     		PDF 54S/74S114 54LS/74LS114 54/74S 54/74LS 74LS114 cpj2 8 pin dip j k flipflop ic

    Untitled

    Abstract: No abstract text available
    Text: 112 CONNECTION DIAGRAM P IN O U T A 54S/74S112 t1" 00 \/&4LS/74LS112 b DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP DESCRIPTION — The '112 features individual J, K, C lo ck and asynchronous Set and C lear inputs to each flip-flop. When the clo ck goes HIGH, the inputs


    OCR Scan     		PDF 54S/74S112 4LS/74LS112 54/74LS 54/74S

    74ls112 pin diagram

    Abstract: 74ls112 pin configuration 74ls112 function table 74LS112 74S112 74ls112 waveform N74LS112N 1N916 74LS N74LS112D
    Text: Signetics 74LS112, S112 Flip-Flops Dual J-K Edge-Triggered Flip-Flop Product Specification Logic Products DESCRIPTION TYPE T h e '1 1 2 is a d u a l J - K n e g a tiv e e d g e - TY P IC A L f HAX trig g e r e d f lip - f lo p fe a tu r in g in d iv id u a l J,


    OCR Scan     		PDF 74LS112, 1N916, 1N3064, 500ns 74ls112 pin diagram 74ls112 pin configuration 74ls112 function table 74LS112 74S112 74ls112 waveform N74LS112N 1N916 74LS N74LS112D

    SN54LS114A

    Abstract: SN54S114 SN74 SN74LS114A SN74S114A LS114
    Text: SN54LS114A, SN54S114, SN74LS114A, SN74S114A DUAL J K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET. COMMON CLEAR, AND COMMON CLOCK MARCH 1973 —R EV ISED MARCH 1988 SN 54LS114A . SN 54S114 SN 74LS114A . SN 74S114A • Fully Buffered to Offer Maximum Isolation


    OCR Scan     		PDF SN54LS114A, SN54S114, SN74LS114A, SN74S114A SN54S114. SN54LS114A SN54S114 SN74 SN74LS114A LS114

    8 pin dip j k flipflop ic

    Abstract: 74LS112P 74LS112D 74LS112PC 74ls112 pin diagram
    Text: NATIONAL SEMICOND {LOGIC} DEE D | b S O H E E • 00b37fl7 S | 112 T-lk-07-0 7 CO NN ECTIO N DIAGRAM PINOUT A 54S/74S112 54LS/74LS112 CPi DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP


    OCR Scan     		PDF 00b37fl7 T-lk-07-0 54S/74S112 54LS/74LS112 54/74S 54/74LS 8 pin dip j k flipflop ic 74LS112P 74LS112D 74LS112PC 74ls112 pin diagram

    74LS113A

    Abstract: tp 2123
    Text: MITSUBISHI LSTTLs M 7 4LS 113 A P DUAL J-K NEGATIVE EDGE-TRIGGERED FLIP FLOP WITH SET DESCRIPTION The PIN CONFIGURATION TOP VIEW M 74LS113A P c o n ta in in g 2 J -K is a sem ico n d u c to r in teg rated c irc u it negative edge-triggered flip -flo p circuits


    OCR Scan     		PDF 74LS113A b2LHfl27 0013Sbl 14-PIN 16-PIN 20-PIN tp 2123

    Untitled

    Abstract: No abstract text available
    Text: SN 54LS112A , S N 54S 112, SN 74LS112A , S N 74S 112A DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP FLOPS W ITH PRESET AND CLEAR D 2 6 6 1 . APRIL 1 9 8 2 - REVISED M A R C H 1 9 8 8 Fully Buffered to Offer Maximum Isolation from External Disturbance r a a SN 54LS 112A , SN 54S 112 . . . J OR W PACKAGE


    OCR Scan     		PDF 54LS112A 74LS112A

    74LS114

    Abstract: N74LS114F N74LS114N N74S114F N74S114N S54LS114F S54LS114W S54S114F S54S114W 74H 14
    Text: 54S/74S114 54LS/74LS114 DESCRIPTION The "114" is a Dual JK N egative EdgeT rig gered F lip -F lo p fe a tu rin g ind iv id u a l J, K, and Set inpu ts and com m on C lo c k and Reset inputs. The Set S d and Reset (R d ) inputs, w hen LOW, set o r reset th e o u tp u ts


    OCR Scan     		PDF 54S/74S114 54LS/74LS114 54H/74H 54S/74S 54LS/74LS 74LS114 N74LS114F N74LS114N N74S114F N74S114N S54LS114F S54LS114W S54S114F S54S114W 74H 14

    74ls112 pin diagram

    Abstract: 74HC112
    Text: GD54/74HC112, GD54/74HCT112 DUAL J-K FLIP-FLOPS WITH PRESET & CLEAR General Description These devices are identical in pinout to the 54/74LS112. They consist of two J-K flip-flops with individual J, K, CLOCK, PRESET, and CLEAR in­ puts. These flip-flops are edge sensitive to the clock


    OCR Scan     		PDF GD54/74HC112, GD54/74HCT112 54/74LS112. 74ls112 pin diagram 74HC112

    IC TTL 7432

    Abstract: 74LS86 gate diagram 7411 3 INPUT AND gate IC 7432 7411 pin diagram 74LS266 IC 7486 74LS series logic gate symbols FL 9014 TTL 74126
    Text: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL-TTL D16 547408, 54H/74H08, 54S/74S08, 54LS/74LS08 54/7409, 54S/74S09, 54LS/74LS09 D18 54/7411, 54H/74H11, 54S/74S11, 54LS/74LS11, 54S/74S15, 54LS/74LS15 D17 9S41 1^1FH [iä| [vii Eòi [T| r»1 Vcc Vcc füi Fai np f i ! Föi lyi rn


    OCR Scan     		PDF 54H/74H08, 54S/74S08, 54LS/74LS08 54S/74S09, 54LS/74LS09 54H/74H21 54LS/74LS21 54S/74S32 54LS/74LS32 54H/74H11, IC TTL 7432 74LS86 gate diagram 7411 3 INPUT AND gate IC 7432 7411 pin diagram 74LS266 IC 7486 74LS series logic gate symbols FL 9014 TTL 74126

    74LS113A

    Abstract: No abstract text available
    Text: AA M O T O R O L A SN54/74LS113A D E S C R IPT IO N — The S N 5 4 L S /7 4 L S 1 13A offers individual J, K, set, and clock inputs. These m onolithic dual flip-flops a re designed so that w h e n th e clock goes HIGH, th e inputs a re enabled and data w ill be


    OCR Scan     		PDF SN54/74LS113A 74LS113A

    Untitled

    Abstract: No abstract text available
    Text: LS TTL DN74LS Series D N 7 4 LS1 1 2 DN74LS112 i0 7 ^ IS ¡ ¡ ^ Dual J-K Negative Edge-Triggered Flip-Flops with Set and Reset H Description P -2 DN 74LS112 contains two negative-edge triggered J-K flipflop circuits, each w ith independent clock-CP, J, K, and


    OCR Scan     		PDF DN74LS DN74LS112 74LS112

    74LS113

    Abstract: S113 equivalent
    Text: 74LS113, S113 Signetics Flip-Flops Dual J-K Edge-Triggered Flip-Flop Product Specification Logic Products DESCRIPTION The '113 is a dual J-K negative edgetriggered flip-flop featuring individual J, K, Set and Clock inputs. The asynchro­ nous Set Su input, when LOW, forces


    OCR Scan     		PDF 74LS113, WF08450S 1N916, 1N3064, 500ns 500ns 74LS113 S113 equivalent

    Untitled

    Abstract: No abstract text available
    Text: MITSUBISHI LSTTLs M 74LS112AP DUAL J-K N EG A TIVE EDGE-TRIGGERED F L IP FLOPS W IT H SET AND RESET DESCRIPTION The M 7 4L S 11 2A P is a semiconductor integrated circuit containing 2 J-K negative edge-triggered flip -flo p circuits w ith discrete terminals fo r clock input T , J and K inputs


    OCR Scan     		PDF 74LS112AP b2LHfl27 0013Sbl

    74LS113

    Abstract: 1N3064 1N916 74LS 74S113 N74LS113N N74S113N S113
    Text: 74LS113, S113 Signetics Flip-Flops Dual J-K Edge-Triggered Flip-Flop Product Specification Logic Products DESCRIPTION T h e '1 1 3 is a d u a l J -K n e g a tive edg e trig g e re d flip -flo p fe a tu rin g ind ivid u a l J, K, S e t and C lo c k inp u ts. T h e a s y n c h ro ­


    OCR Scan     		PDF 74LS113, 1N916, 1N3064, 500ns 74LS113 1N3064 1N916 74LS 74S113 N74LS113N N74S113N S113

    74LS113

    Abstract: 1N3064 1N916 74LS 74S113 N74LS113N N74S113N S113
    Text: 74LS113, S 'it e Signetics Flip-Flops Dual J-K Edge-Triggered Flip-Flop Product Specification Logic Products DESCRIPTION T h e '1 1 3 is a dual J -K n e g a tive e dg e trig g e re d flip -flo p fe a tu rin g individ u a l J, K, S e t a n d C lo c k inp u ts. T h e a s y n c h ro ­


    OCR Scan     		PDF 74LS113, tr113, 1N916, 1N3064, 500ns 74LS113 1N3064 1N916 74LS 74S113 N74LS113N N74S113N S113

    74LSOO

    Abstract: PRESET 1M 1S2074 HD74LS112
    Text: H D 74LS112. Dual J-K Negative-edge-triggered Flip-Flops with Preset and Clear •BLOCK D IA G R A M (^) « P IN ARRANGEMENT ■RECOMMENDED OPERATING CONDITIONS Sym bol Item f 'l t 'k C lo c k fre q u e n c y C lo c k H igh min ty p m ax U n it - 30 M Hz


    OCR Scan     		PDF HD74LS112. QQ14CI14 DG-14 06max 20-IU8 OG-16 DG-24 74LSOO PRESET 1M 1S2074 HD74LS112