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Catalog Datasheet	MFG & Type	Document Tags	PDF
Untitled Abstract: No abstract text available Text: Hierarchically Accessing 1149.1 Applications in a System Environment Lee Whetsel Texas Instruments Incorporated  1993 IEEE. Reprinted, with permission, from Proceedings of International Test Conference, Baltimore, Maryland, October 17–21, 1993. SCTA033	Original	SCTA033	PDF
conference system Abstract: semiconductor Text: Hierarchically Accessing 1149.1 Applications in a System Environment Lee Whetsel Texas Instruments Incorporated Senior Member Technical Staff Semiconductor Group SCTA033  1993 IEEE. Reprinted, with permission, from Proceedings of International Test Conference, Baltimore, Maryland, October 17–21, 1993.	Original	SCTA033 conference system semiconductor	PDF
scta033 Abstract: No abstract text available Text: Hierarchically Accessing 1149.1 Applications in a System Environment Lee Whetsel Texas Instruments Incorporated  1993 IEEE. Reprinted, with permission, from Proceedings of International Test Conference, Baltimore, Maryland, October 17–21, 1993. SCTA033	Original	SCTA033 scta033	PDF
dct 814 Abstract: clock tree balancing IC 2073 astro tools B2008 project ips ips works astro mb HIERARCHICALLY astro place and routing Text: Designing Hierarchically Reusable Digital IPs Using DC-T/ICC Flow James Deng Michael Lai Ninh Ngo Keith Duwel Kevin Huang Michael Zheng Richard Price Altera Corporation San Jose, California, USA www.altera.com Liang Xu, Sridhar Panchapakesan, Pallavi Padala	Original	45-nm dct 814 clock tree balancing IC 2073 astro tools B2008 project ips ips works astro mb HIERARCHICALLY astro place and routing	PDF
MC 4011 BCP Abstract: PKT 4113 API ncp 6131 SWITCHING SYSTEMS INTERNATIONAL sqm 225 leach 1522 her 4541 MSP SNCP t 1451 n 52 toh SWITCHING SYSTEMS INTERNATIONAL sqm 350 k2400 EQUIVALENT Text: EtherPHAST -24 Device 2x OC-12/STM-4 SONET/SDH Ethernet Mapper TXC-06745 DATA SHEET TXC-06745-MB, Ed. 2 February 2006 FEATURES APPLICATIONS • Client Interfaces: 2x GMII/24x SMII/4x TBI/MPI 24 channel packet all pin shared • Two serial Gigabit Ethernet (1.25 Gbit/s) ports with integrated CRSU/SerDes (8B/10B)	Original	OC-12/STM-4 TXC-06745 TXC-06745-MB, GMII/24x 8B/10B) 8B/10B 32-bit EtherPHAST-24 MC 4011 BCP PKT 4113 API ncp 6131 SWITCHING SYSTEMS INTERNATIONAL sqm 225 leach 1522 her 4541 MSP SNCP t 1451 n 52 toh SWITCHING SYSTEMS INTERNATIONAL sqm 350 k2400 EQUIVALENT	PDF
6206a Abstract: K-Line transceiver w1p 84 st10f2xx sigma asc 333 24 pin K-line ST10F276E W1P 59 st10 Bootstrap st10273e Text: ST10F276E 16-bit MCU with MAC unit 832 Kbyte Flash memory and 68 Kbyte RAM Datasheet − production data Features • ■ ■ ■ ■ ■ Highly performance 16-bit CPU with DSP functions – 31.25ns instruction cycle time at 64MHz max CPU clock – Multiply/accumulate unit MAC 16 x 16-bit	Original	ST10F276E 16-bit 64MHz 40-bit 32-bit 6206a K-Line transceiver w1p 84 st10f2xx sigma asc 333 24 pin K-line ST10F276E W1P 59 st10 Bootstrap st10273e	PDF
CMP14 Abstract: No abstract text available Text: FUJITSU SEMICONDUCTOR CONTROLLER MANUAL CM71-10134-1E FR 60 32-BIT MICROCONTROLLER MB91470/480 Series HARDWARE MANUAL FR 60 32-BIT MICROCONTROLLER MB91470/480 Series HARDWARE MANUAL Be sure to refer to the “Check Sheet” for the latest cautions on development.	Original	CM71-10134-1E 32-BIT MB91470/480 32-trol 0000B, 0018H) CMP14	PDF
AFS600-FG256 Abstract: zo 103 ma 75 607 A54 ZENER flashpro3 schematic mark AT0 Unipolar PC atx 400 P4 power supply diagram zener Diode B23 PQ208 QN108 QN180 Text: Preliminary v1.7 Actel Fusion Mixed-Signal FPGAs Family with Optional ARM® Support Features and Benefits – Frequency: Input 1.5–350 MHz, Output 0.75–350 MHz Low Power Consumption High-Performance Reprogrammable Flash Technology • • • • • Single 3.3 V Power Supply with On-Chip 1.5 V Regulator	Original	130-nm, 128-Bit AFS600-FG256 zo 103 ma 75 607 A54 ZENER flashpro3 schematic mark AT0 Unipolar PC atx 400 P4 power supply diagram zener Diode B23 PQ208 QN108 QN180	PDF
diode T35 12H Abstract: ST10F269Z2Q6 ST10F269Q ST10F269Z2T3 PQFP144 ST10F269 TQFP144 diode t318 BB126 st10 Bootstrap Text: ST10F269 16-BIT MCU WITH MAC UNIT, 128K to 256K BYTE FLASH MEMORY AND 12K BYTE RAM DATASHEET • ■ 2K Byte Internal RAM 16 CPU-Core and MAC Unit Watchdog 16 10K Byte XRAM CAN1_RXD CAN1_TXD CAN1 CAN2_RXD CAN2_TXD CAN2 PEC Oscillator and PLL 16 Interrupt Controller	Original	ST10F269 16-BIT 256KByte TQFP144 F269-Q3 diode T35 12H ST10F269Z2Q6 ST10F269Q ST10F269Z2T3 PQFP144 ST10F269 TQFP144 diode t318 BB126 st10 Bootstrap	PDF
Untitled Abstract: No abstract text available Text: Standard Products UTCAM-EngineTM Dynamically Configurable Content Addressable Memory Engine Preliminary Datasheet Nov. 1998 FEATURES External Memory q Addresses up to 8 mega words of SSRAM Performance and Flexibility q Rapid association matching for exact match seeks	Original	32-bit 64-bit 254MM MS-029. 634MM. 256-lead	PDF
A54 ZENER Abstract: AFS600-FG256 mark AT0 QN108 CORE8051 bipolar ROM Text: v2.0 Actel Fusion Family of Mixed-Signal FPGAs Features and Benefits In-System Programming ISP and Security High-Performance Reprogrammable Flash Technology Advanced Digital I/O • • • • • Secure ISP with 128-Bit AES via JTAG • FlashLock® to Secure FPGA Contents	Original	128-Bit 130-nm, A54 ZENER AFS600-FG256 mark AT0 QN108 CORE8051 bipolar ROM	PDF
SX-550-2701 Abstract: SX-550-1701 Atheros AR5413 AR5413 data circuit schematics satellite connector circuit diagram of wifi wireless router HALO TG110 Atheros FC-618SM atheros 9201 Text: SX-550 Embedded Intelligent Module Developer’s Reference Guide Revision L 2009 Silex Technology America, Inc. All rights reserved. March 2009 Silex Technology America SPECIFICALLY DISCLAIMS THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS OF THIS PRODUCT FOR A PARTICULAR PURPOSE. Silex	Original	SX-550 SX-550-2701 SX-550-1701 Atheros AR5413 AR5413 data circuit schematics satellite connector circuit diagram of wifi wireless router HALO TG110 Atheros FC-618SM atheros 9201	PDF
VENDING MACHINE vhdl code Abstract: vhdl code for vending machine vending machine using fsm vhdl code for soda vending machine vhdl code for vending machine with 7 segment display VENDING MACHINE vhdl vhdl code for half adder vhdl code for flip-flop Cypress VHDL vending machine code vhdl implementation for vending machine Text: 3125/C CY3120/CY3125/CY3120J Warp2 VHDL Compiler for CPLDs Features • VHDL IEEE 1076 and 1164 high-level language compiler — Facilitates device-independent design • Timing simulation provided with Active-HDL Sim from Aldec (PC only): — Graphical waveform simulator	Original	3125/C CY3120/CY3125/CY3120J VENDING MACHINE vhdl code vhdl code for vending machine vending machine using fsm vhdl code for soda vending machine vhdl code for vending machine with 7 segment display VENDING MACHINE vhdl vhdl code for half adder vhdl code for flip-flop Cypress VHDL vending machine code vhdl implementation for vending machine	PDF
GPR circuit schematic diagram full Abstract: DP43 T308 ST10F269-T6 ST*10f269-q3 m29F ST10F269-T3 TQFP144 f082h st10 Bootstrap Text: ST10F269-T3 16-BIT MCU WITH MAC UNIT, 256K BYTE FLASH MEMORY AND 12K BYTE RAM March 2003 FAIL-SAFE PROTECTION – PROGRAMMABLE WATCHDOG TIMER – OSCILLATOR WATCHDOG • ■ ON-CHIP BOOTSTRAP LOADER CLOCK GENERATION – ON-CHIP PLL – DIRECT OR PRESCALED CLOCK INPUT	Original	ST10F269-T3 16-BIT 144-PIN F269-T3 GPR circuit schematic diagram full DP43 T308 ST10F269-T6 ST*10f269-q3 m29F ST10F269-T3 TQFP144 f082h st10 Bootstrap	PDF

verilog code for vending machine Abstract: verilog code for two 32 bit adder verilog code for vending machine using finite state machine vending machine verilog HDL file verilog code for digital clock verilog code finite state machine complete fsm of vending machine verilog code for 16 bit ram vhdl code for vending machine digital clock verilog code Text: 3115/C CY3110/CY3115/CY3110J Warp2 Verilog Compiler for CPLDs Features — Ability to probe internal nodes — Display of inputs, outputs, and High Z signals in different colors • Verilog IEEE 1364 high-level language compiler — Facilitates device independent design	Original	3115/C CY3110/CY3115/CY3110J verilog code for vending machine verilog code for two 32 bit adder verilog code for vending machine using finite state machine vending machine verilog HDL file verilog code for digital clock verilog code finite state machine complete fsm of vending machine verilog code for 16 bit ram vhdl code for vending machine digital clock verilog code	PDF
mt 1389 de Abstract: MLC 8050 Transistor mlc 8050 IC01 -P10 Replace philips tea 1090 8*8 led dot MATRIX Driver i2c tea 1601 t MDT 1692 LT 542 seven segment display data sheet mt 1389 Text: REJ09B0360-0100 32 SH7764 Group Hardware Manual Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series SH77641 SH77640 Rev.1.00 Revision Date: Nov. 22, 2007 R5S77641 R5S77640 Rev. 1.00 Nov. 22, 2007 Page ii of lvi Notes regarding these materials	Original	REJ09B0360-0100 SH7764 32-Bit SH77641 SH77640 R5S77641 R5S77640 mt 1389 de MLC 8050 Transistor mlc 8050 IC01 -P10 Replace philips tea 1090 8*8 led dot MATRIX Driver i2c tea 1601 t MDT 1692 LT 542 seven segment display data sheet mt 1389	PDF
CB4CLE Abstract: cb4re CB8CLED cb8cle CB4CLED X74-160 x4202 CB16CE sr4cled 2 bit magnitude comparator using 2 xor gates Text: ON LIN E R LIBRARIES G UI DE T ABL E OF CONT ENT S INDEX GO T O OT HER BOOKS 0 4 0 1410 Copyright 1993-1995 Xilinx Inc. All Rights Reserved. Contents Chapter 1 Xilinx Unified Libraries Overview .	Original		PDF
LC1 D12 wiring diagram Abstract: vhdl code for 8 bit ODD parity generator 74139 Dual 2 to 4 line decoder TTL XOR2 tig ac inverter circuit cd4rle LC1 D12 P7 CB4CLED sr4cled CB16CE Text: Libraries Guide Xilinx Unified Libraries Selection Guide Design Elements ACC1 to BYPOSC Design Elements (CAPTURE_SPARTAN2 to DECODE64) Design Elements (F5MAP to FTSRLE) Design Elements (GCLK to KEEPER) Design Elements (LD to NOR16) Design Elements (OAND2 to OXOR2)	Original	DECODE64) NOR16) ROM32X1) XC2064, XC3090, XC4005, XC5210, XC-DS501 X7706 XC5200 LC1 D12 wiring diagram vhdl code for 8 bit ODD parity generator 74139 Dual 2 to 4 line decoder TTL XOR2 tig ac inverter circuit cd4rle LC1 D12 P7 CB4CLED sr4cled CB16CE	PDF
structure processor pentium3 Abstract: laptops power ic S5U1C33001H S1C33000 S1C33L01 S5U1C33001C em 328 epson S1C33 BT 342 project 29LV800te Text: CMOS 32-BIT SINGLE CHIP MICROCOMPUTER S5U1C33001C Manual C/C+ Compiler Package for S1C33 Family (Ver. 3.3.0) NOTICE No part of this material may be reproduced or duplicated in any form or by any means without the written permission of Seiko Epson. Seiko Epson reserves the right to make changes to this material without notice. Seiko Epson does not	Original	32-BIT S5U1C33001C S1C33 structure processor pentium3 laptops power ic S5U1C33001H S1C33000 S1C33L01 em 328 epson BT 342 project 29LV800te	PDF
mini project using ic 555 Abstract: S1C17602 S5U1C17001C S1C17704 GNU17 08055F S1C17801 S5U1C17001H S1C17 mini project using ic 555 for practice purpose Text: CMOS 16-BIT SINGLE CHIP MICROCOMPUTER S5U1C17001C Manual C Compiler Package for S1C17 Family (Ver. 1.5.0) NOTICE No part of this material may be reproduced or duplicated in any form or by any means without the written permission of Seiko Epson. Seiko Epson reserves the right to make changes to this material without notice. Seiko Epson does not	Original	16-BIT S5U1C17001C S1C17 mini project using ic 555 S1C17602 S1C17704 GNU17 08055F S1C17801 S5U1C17001H mini project using ic 555 for practice purpose	PDF
AXP 188 ba Abstract: 21071-DA 2mb1100 AXP 188 IC 5188b RSAD 5111 1M 21071-BA 82378IB 21071AA d327c Text: m DECchip 21071-AA, 21072-AA Core Logic Data Sheet m A p ril 1994 21071-AA, 21072-A A Features: • Supports the entire fam ily of the DECchip 21064 Alpha AXP m icroprocessors • DECchip 21071-AA: 128-bit cache/64-bit memory • DECchip 21072-AA: 128-bit cache/128-bit	OCR Scan	21071-AA, 1072-A 128-bit cache/64-bit 21072-AA: cache/128-bit 32-bit parity/32-bit 21072-AA AXP 188 ba 21071-DA 2mb1100 AXP 188 IC 5188b RSAD 5111 1M 21071-BA 82378IB 21071AA d327c	PDF
SERVICE MANUAL tv TCL Abstract: ED06 ED08 internal circuit diagram for ic 4047 C161 C161RI C166 SAB-C161RI-LF SAB-C161RI-LM SAF-C161RI-LM Text: SIEMENS Data Sheet 0198 Advance Information This Material C o p yright ed By Its Respec tive Ma nufac turer C161RI Revision History: 1998-01 A dvance Inform ation P revious Releases: 1997-12 A dvance Inform ation P age S ubjects 7 RSTIN description com pleted with bidirectional reset.	OCR Scan	C161RI D-81541 25max C161RI P-TQFP-100-1 DTH14x SERVICE MANUAL tv TCL ED06 ED08 internal circuit diagram for ic 4047 C161 C166 SAB-C161RI-LF SAB-C161RI-LM SAF-C161RI-LM	PDF
Untitled Abstract: No abstract text available Text: DECchip 21171 Core Logic Chipset Technical Reference Manual Order Number: EC-QE18A-TE Revision/Update Information: Digital Equipment Corporation Maynard, Massachusetts aam i3t. 0 0 3 3 7 3 3 0 22 Preliminary—Subject to Change Ju ne 1995 W hile D igital believes th e inform ation in th is publication is correct as of th e d ate of publication,	OCR Scan	EC-QE18A-TE HF3-15A	PDF
Untitled Abstract: No abstract text available Text: FU JITSU UHB SERIES 1.5p CMOS GATE ARRAYS MB62XXXX MB60XXXX Septem ber 1988 Edition 1.1 DESCRIPTION The UHB series o f 1 .5-m icron CMOS gate arrays Is a highly Integrated low -pow er, ultra high-speed product fam ily th a t derives its enhanced perform ance and increased user flexibility fro m the use of a system -proven, dual-colum n gate s tru ctu re and 2-layer	OCR Scan	MB62XXXX MB60XXXX FPT-160PM01) 40-LEAD DIP-40P-M01) 54JTYP 40006S-1C	PDF

HIERARCHICALLY Search Results

HIERARCHICALLY Datasheets Context Search

Untitled

conference system

scta033

dct 814

MC 4011 BCP

6206a

CMP14

AFS600-FG256

diode T35 12H

Untitled

A54 ZENER

SX-550-2701

VENDING MACHINE vhdl code

GPR circuit schematic diagram full

verilog code for vending machine

mt 1389 de

CB4CLE

LC1 D12 wiring diagram

structure processor pentium3

mini project using ic 555

AXP 188 ba

SERVICE MANUAL tv TCL

Untitled

Untitled