Please enter a valid full or partial manufacturer part number with a minimum of 3 letters or numbers

    J K FLIP FLOP IC Search Results

    J K FLIP FLOP IC Result Highlights (5)

    Part ECAD Model Manufacturer Description Download Buy
    74ACT11175DW Rochester Electronics LLC D Flip-Flop, Visit Rochester Electronics LLC Buy
    SN54LS107J Rochester Electronics LLC J-K Flip-Flop Visit Rochester Electronics LLC Buy
    MC2125FB2 Rochester Electronics LLC MC2125 - J-K Flip-Flop Visit Rochester Electronics LLC Buy
    SN74HC534DW-G Rochester Electronics LLC 74HC534 - Octal D-Type Flip-Flop Visit Rochester Electronics LLC Buy
    74LS574N Rochester Electronics 74LS574 - Octal D-Type Flip Flop Visit Rochester Electronics Buy

    J K FLIP FLOP IC Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    Untitled

    Abstract: No abstract text available
    Text: IDT74LVC112A 3.3V CMOS DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP INDUSTRIAL TEMPERATURE RANGE 3.3V CMOS DUAL IDT74LVC112A NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP WITH CLEAR AND PRESET, 5 VOLT TOLERANT I/O DESCRIPTION: FEATURES: This dual negative-edge-triggered J-K flip-flop is built using advanced


    Original     		PDF IDT74LVC112A

    8 way flip-flop ic

    Abstract: IDT74LVC112A LVC112A
    Text: IDT74LVC112A 3.3V CMOS DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP INDUSTRIAL TEMPERATURE RANGE 3.3V CMOS DUAL IDT74LVC112A NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP WITH CLEAR AND PRESET, 5 VOLT TOLERANT I/O DESCRIPTION: FEATURES: This dual negative-edge-triggered J-K flip-flop is built using advanced


    Original     		PDF IDT74LVC112A 8 way flip-flop ic IDT74LVC112A LVC112A

    C1995

    Abstract: DM74ALS DM74ALS109A DM74ALS109AM DM74ALS109AN LS109 M16A N16A
    Text: DM74ALS109A Dual J-K PositiveEdge-Triggered Flip-Flop with Preset and Clear General Description Features The DM54ALS109A is a dual edge-triggered flip-flop Each flip-flop has individual J K clock clear and preset inputs and also complementary Q and Q outputs


    Original     		PDF DM74ALS109A DM54ALS109A C1995 DM74ALS DM74ALS109AM DM74ALS109AN LS109 M16A N16A

    LCX112

    Abstract: 74LCX112 74LCX112M 74LCX112MTC 74LCX112SJ M16A M16D MTC16 DSA0031497
    Text: Revised August 1998 74LCX112 Low Voltage Dual J-K Negative Edge-Triggered Flip-Flop with 5V Tolerant Inputs General Description Features The LCX112 is a dual J-K flip-flop. Each flip-flop has independent J, K, PRESET, CLEAR, and CLOCK inputs with Q, Q outputs. These devices are edge sensitive and change


    Original     		PDF 74LCX112 LCX112 74LCX112 74LCX112M 74LCX112MTC 74LCX112SJ M16A M16D MTC16 DSA0031497

    LCX112

    Abstract: MTC16 74LCX112 74LCX112M 74LCX112MTC 74LCX112SJ M16A M16D
    Text: Revised February 2001 74LCX112 Low Voltage Dual J-K Negative Edge-Triggered Flip-Flop with 5V Tolerant Inputs General Description Features The LCX112 is a dual J-K flip-flop. Each flip-flop has independent J, K, PRESET, CLEAR, and CLOCK inputs with Q, Q outputs. These devices are edge sensitive and change


    Original     		PDF 74LCX112 LCX112 74LCX112 MTC16 74LCX112M 74LCX112MTC 74LCX112SJ M16A M16D

    74LCX112

    Abstract: 74LCX112M 74LCX112MTC 74LCX112SJ LCX112 M16A M16D MTC16
    Text: Revised March 1999 74LCX112 Low Voltage Dual J-K Negative Edge-Triggered Flip-Flop with 5V Tolerant Inputs General Description Features The LCX112 is a dual J-K flip-flop. Each flip-flop has independent J, K, PRESET, CLEAR, and CLOCK inputs with Q, Q outputs. These devices are edge sensitive and change


    Original     		PDF 74LCX112 LCX112 74LCX112 74LCX112M 74LCX112MTC 74LCX112SJ M16A M16D MTC16

    Untitled

    Abstract: No abstract text available
    Text: Revised February 2001 74LCX112 Low Voltage Dual J-K Negative Edge-Triggered Flip-Flop with 5V Tolerant Inputs General Description Features The LCX112 is a dual J-K flip-flop. Each flip-flop has independent J, K, PRESET, CLEAR, and CLOCK inputs with Q, Q outputs. These devices are edge sensitive and change


    Original     		PDF 74LCX112 LCX112 74LCX112

    k0215

    Abstract: 74ALS112A 74ALS 74ALS112AD 74ALS112AN
    Text: INTEGRATED CIRCUITS 74ALS112A Dual J-K negative edge-triggered flip-flop Product specification IC05 Data Handbook Philips Semiconductors 1996 June 27 Philips Semiconductors Product specification Dual J-K negative edge-triggered flip-flop DESCRIPTION 74ALS112A


    Original     		PDF 74ALS112A 74ALS112A, k0215 74ALS112A 74ALS 74ALS112AD 74ALS112AN

    DM74ALS

    Abstract: DM74ALS109A DM74ALS109AM DM74ALS109AN LS109 M16A N16A DM74ALS109
    Text: DM74ALS109A Dual J-K Positive-Edge-Triggered Flip-Flop with Preset and Clear General Description Features The DM54ALS109A is a dual edge-triggered flip-flop. Each flip-flop has individual J, K, clock, clear and preset inputs, and also complementary Q and Q outputs.


    Original     		PDF DM74ALS109A DM54ALS109A DM74ALS DM74ALS109A DM74ALS109AM DM74ALS109AN LS109 M16A N16A DM74ALS109

    Untitled

    Abstract: No abstract text available
    Text: Signetics 54F113 Flip-Flop Dual J-K Negative Edge-Triggered Flip-Flop Without Reset Product Specification Military Logic Products DESCRIPTION The 54F113 is a dual J-K negative edge-triggered flip-flop featuring indi­ vidual J, K, Set and Clock inputs. The


    OCR Scan     		PDF 54F113 54F113 500ns

    TC40H076AP

    Abstract: AH120 A140S TC40H076P TC40H76AP
    Text: TOSHIBA INTEGRATED CIRCUIT TECHNICAL DATA Æ TC40H076P/F TC40H076AP/AF C2MOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC TC40H076 TC40H076A DUAL J-K FLIP-FLOP PULSE TRIGGER TYPE DUAL J-K FLIP-FLOP (EDGE TRIGGER TYPE) The TC40H076 is a dual J-K flip-flop with


    OCR Scan     		PDF TC40H076P/F TC40H076AP/AF TC40H076 TC40H076A TC40H076A, 3d13a-p) TC40H076AP AH120 A140S TC40H076P TC40H76AP

    14027B

    Abstract: HD14027B
    Text: HD14027B Dual J - K Flip Flop The HD14027B dual J-K flip-flop has independent J, K, Clock C , Set(S) and Reset(R) inputs for each flip-flop. These devices may be used in control, register, or toggle functions. • PIN ARRANGEMENT ■ FEATURES • • •


    OCR Scan     		PDF HD14027B HD14027B CD4027B MC14027B K20ns 14027B

    Untitled

    Abstract: No abstract text available
    Text: m jé National Semiconductor DM74AS109 Dual J-K Positive-Edge-Triggered Flip-Flop with Preset and Clear General Description Features The ’AS109 is a dual edge-triggered flip-flop. Each flip-flop has individual J, K, clock, clear and preset inputs, and also


    OCR Scan     		PDF DM74AS109 AS109

    Untitled

    Abstract: No abstract text available
    Text: MOTOROLA DUAL J-K FLIP-FLOP MC14027B The MC14Q27B dual J-K flip-flop has independent J, K, Clock {Q, Set S and Reset |R) inputs for each flip-flop. These devices may be used in control, register, or toggle functions. CMOS SSI • • Diode Protection on A ll Inputs


    OCR Scan     		PDF MC14Q27B MC14027B

    Untitled

    Abstract: No abstract text available
    Text: Revised August 1998 SE M IC O N D U C TO R TM 74LCX112 Low Voltage Dual J-K Negative Edge-Triggered Flip-Flop with 5V Tolerant Inputs General Description Features The LCX112 is a dual J-K flip-flop. Each flip-flop has inde£endent J, K, PRESET, CLEAR, and CLOCK inputs with Q,


    OCR Scan     		PDF 74LCX112 LCX112 74LCX112

    ECL 10135

    Abstract: 10135 jk flipflop 425 10135F 10135N 10135dc ecl 10K signetics
    Text: Signetics 10135 Flip-Flop Dual J-K Master-Slave Flip-Flop P roduct Specification ECL Products DESCRIPTION The 10135 is a Dual Master-Slave DC coupled J-K Flip-Flop. It contains a com­ mon clock and separate J-K inputs which do not affect the output when the


    OCR Scan     		PDF 10135N 10135F 800mVp-p 500ns ECL 10135 10135 jk flipflop 425 10135F 10135N 10135dc ecl 10K signetics

    Untitled

    Abstract: No abstract text available
    Text: S E M IC O N D U C T O R Revised March 1999 TM 74LCX112 Low Voltage Dual J-K Negative Edge-Triggered Flip-Flop with 5V Tolerant Inputs General Description Features The LCX112 is a dual J-K flip-flop. Each flip-flop has inde£endent J, K, PRESET, C LEAR , and C LO C K inputs with Q,


    OCR Scan     		PDF 74LCX112 LCX112

    Untitled

    Abstract: No abstract text available
    Text: 54LS109 Signetics Flip-Flop Dual J-K Positive Edge-Triggered Flip-Flop Product Specification Military Logic Products DESCRIPTION The 54LS109 is a dual positive edge-trig­ gered JK-type flip-flop featuring individual J, K, Clock, Set and Reset inputs; also


    OCR Scan     		PDF 54LS109 54LS109 54LSXXX 500ns S15ns 1N916 1N3064,

    Untitled

    Abstract: No abstract text available
    Text: MC14025B See Page 6-5 MOTOROLA MCM025U8 See Page 6-14 MC14027B DUAL J-K FLIP-FLOP The M C14027B dual J-K flip-flop has independent J , K , Clock C , Set (S) and Reset (R ) inputs for each flip-flop. These devices may be used in control, register, or toggle functions.


    OCR Scan     		PDF MC14025B MCM025U8 MC14027B C14027B

    74LCX112

    Abstract: 74LCX112M 74LCX112MTC 74LCX112SJ LCX112 M16A M16D MTC16
    Text: S E M IC O N D U C T O R Revised March 1999 TM 74LCX112 Low Voltage Dual J-K Negative Edge-Triggered Flip-Flop with 5V Tolerant Inputs General Description Features T he LCX112 is a dual J-K flip-flop. Each flip-flop has inde­ pendent J, K, PRESET, C LEAR, and C LO C K inputs with Q,


    OCR Scan     		PDF 74LCX112 LCX112 74LCX112 74LCX112M 74LCX112MTC 74LCX112SJ M16A M16D MTC16

    74ls112 pin configuration

    Abstract: 74ls112 function table 74LS112 74S112
    Text: Signetics 74LS112, S112 Flip-Flops Dual J-K Edge-Triggered Flip-Flop Product Specification Logic Products DESCRIPTION The '112 is a dual J-K negative edgetriggered flip-flop featuring individual J, K, Clock, Set and Reset inputs. The Set So and Reset (R q) inputs, when LOW,


    OCR Scan     		PDF 74LS112, 1N916, 1N3064, 500ns 500ns 74ls112 pin configuration 74ls112 function table 74LS112 74S112

    jk flip flop 7476

    Abstract: 7476 PIN DIAGRAM 7476 7476 ttl 7476 PIN DIAGRAM input and output TTL 74ls76 pin diagram of 7476 PIN CONFIGURATION 7476 7476 J-K Flip-Flop pin diagram of ttl 7476
    Text: Signetics 7476, LS76 Flip-Flops Dual J-K Flip-Flop Product Specification Logic Products DESCRIPTION The '76 is a dual J-K flip-flop with individual J, K, Clock, Set and Reset inputs. The 7476 is positive pulse-trig­ gered. JK information is loaded into the


    OCR Scan     		PDF 74LS76 1N916, 1N3064, 500ns jk flip flop 7476 7476 PIN DIAGRAM 7476 7476 ttl 7476 PIN DIAGRAM input and output TTL 74ls76 pin diagram of 7476 PIN CONFIGURATION 7476 7476 J-K Flip-Flop pin diagram of ttl 7476

    74LS412

    Abstract: 74LS41 74ls112n 74LS112D 74ls112 pin configuration 74LS112
    Text: 74LS112, S112 Signetics Flip-Flops Dual J-K Edge-Triggered Flip-Flop Product Specification Logic Products DESCRIPTION The '112 is a dual J-K negative edgetriggered flip-flop featuring individual J, K, Clock, Set and Reset inputs. The Set So and Reset (R q) inputs, when LOW,


    OCR Scan     		PDF 74LS112, 500ns 500ns 74LS412 74LS41 74ls112n 74LS112D 74ls112 pin configuration 74LS112

    Untitled

    Abstract: No abstract text available
    Text: 54F109 Signetics Flip-Flop Dual J-K Positive Edge-Triggered Flip-Flop Product Specification Military Logic Products DESCRIPTION The 54F109 is a dual positive edge-trig­ gered JK-type flip-flop featuring individual J, K, Clock, Set and Reset inputs, and complementary Ü outputs.


    OCR Scan     		PDF 54F109 54F109 500ns