Untitled
Abstract: No abstract text available
Text: 74LVC1G14 Single Schmitt-trigger inverter Rev. 12 — 6 August 2012 Product data sheet 1. General description The 74LVC1G14 provides the inverting buffer function with Schmitt-trigger input. It is capable of transforming slowly changing input signals into sharply defined, jitter-free
|
Original
|
74LVC1G14
74LVC1G14
|
PDF
|
MARKING V7 6-PIN
Abstract: No abstract text available
Text: 74LVC3G14 Triple inverting Schmitt trigger with 5 V tolerant input Rev. 11 — 6 July 2012 Product data sheet 1. General description The 74LVC3G14 provides three inverting buffers with Schmitt trigger input. It is capable of transforming slowly changing input signals into sharply defined, jitter-free output signals.
|
Original
|
74LVC3G14
74LVC3G14
MARKING V7 6-PIN
|
PDF
|
74AUP1G126
Abstract: 74AUP1G32 JESD22-A114E 74AUP1T1326
Text: 74AUP1T1326 Low-power dual supply buffer/line driver; 3-state Rev. 01 — 20 January 2009 Product data sheet 1. General description The 74AUP1T1326 is a high-performance, low-power, low-voltage, single-bit, dual supply buffer/line driver with output enable circuitry.
|
Original
|
74AUP1T1326
74AUP1T1326
74AUP1G32
74AUP1G126.
74AUP1G126
JESD22-A114E
|
PDF
|
74LVC3G14
Abstract: 74LVC3G14DC 74LVC3G14DP 74LVC3G14GM 74LVC3G14GT JESD22-A114E MO-187
Text: 74LVC3G14 Triple inverting Schmitt trigger with 5 V tolerant input Rev. 07 — 12 June 2008 Product data sheet 1. General description The 74LVC3G14 provides three inverting buffers with Schmitt trigger action. The inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of
|
Original
|
74LVC3G14
74LVC3G14
74LVC3G14DC
74LVC3G14DP
74LVC3G14GM
74LVC3G14GT
JESD22-A114E
MO-187
|
PDF
|
74AUP1G58
Abstract: 74AUP1G58GF 74AUP1G58GM JESD22-A114E
Text: 74AUP1G58 Low-power configurable multiple function gate Rev. 02 — 26 March 2009 Product data sheet 1. General description The 74AUP1G58 provides configurable multiple functions. The output state is determined by eight patterns of 3-bit input. The user can choose the logic functions AND, OR, NAND,
|
Original
|
74AUP1G58
74AUP1G58
74AUP1G58GF
74AUP1G58GM
JESD22-A114E
|
PDF
|
74LV374
Abstract: 74HC374 74HCT374 74LV374D 74LV374N DIP20 JESD22-A114E SO20 SSOP20
Text: 74LV374 Octal D-type flip-flop; positive edge-trigger; 3-state Rev. 02 — 14 May 2009 Product data sheet 1. General description The 74LV374 is an octal D-type flip-flop featuring separate D-type inputs for each flip-flop and 3-state outputs for bus-oriented applications. A clock input CP and an output enable
|
Original
|
74LV374
74LV374
74HC374
74HCT374.
74HCT374
74LV374D
74LV374N
DIP20
JESD22-A114E
SO20
SSOP20
|
PDF
|
74LVC1G58
Abstract: 74LVC1G58GF 74LVC1G58GM 74LVC1G58GV 74LVC1G58GW JESD22-A114E marking code 5
Text: 74LVC1G58 Low-power configurable multiple function gate Rev. 04 — 27 April 2009 Product data sheet 1. General description The 74LVC1G58 provides configurable multiple functions. The output state is determined by eight patterns of 3-bit input. The user can choose the logic functions AND, OR, NAND,
|
Original
|
74LVC1G58
74LVC1G58
74LVC1G58GF
74LVC1G58GM
74LVC1G58GV
74LVC1G58GW
JESD22-A114E
marking code 5
|
PDF
|
dhvqfn14 footprint
Abstract: 74AHC14 74AHCT14 sot762 footprint 74AHC14-74AHCT14 74AHC 74AHC14D 74AHC14PW 74AHCT 74AHCT14D
Text: INTEGRATED CIRCUITS DATA SHEET 74AHC14; 74AHCT14 Hex inverting Schmitt trigger Product specification Supersedes data of 1999 Sep 27 2003 May 26 Philips Semiconductors Product specification Hex inverting Schmitt trigger 74AHC14; 74AHCT14 FEATURES DESCRIPTION
|
Original
|
74AHC14;
74AHCT14
74AHC14
74AHCT14
74AHC
74AHCT
dhvqfn14 footprint
sot762 footprint
74AHC14-74AHCT14
74AHC14D
74AHC14PW
74AHCT14D
|
PDF
|
HEF40106BP
Abstract: HEF40106B HEF40106BT HEF40106 MO-001
Text: HEF40106B Hex inverting Schmitt trigger Rev. 4 — 15 November 2010 Product data sheet 1. General description The HEF40106B provides six inverting buffers. Each input has a Schmitt trigger circuit. The inverting buffer switches at different points for positive-going and negative-going
|
Original
|
HEF40106B
HEF40106B
HEF40106BP
HEF40106BT
HEF40106
MO-001
|
PDF
|
74LVC1G57
Abstract: 74LVC1G57GF 74LVC1G57GM 74LVC1G57GV 74LVC1G57GW
Text: 74LVC1G57 Low-power configurable multiple function gate Rev. 4 — 15 October 2010 Product data sheet 1. General description The 74LVC1G57 provides configurable multiple functions. The output state is determined by eight patterns of 3-bit input. The user can choose the logic functions AND, OR, NAND,
|
Original
|
74LVC1G57
74LVC1G57
74LVC1G57GF
74LVC1G57GM
74LVC1G57GV
74LVC1G57GW
|
PDF
|
74AUP2G14
Abstract: 74AUP2G14GF 74AUP2G14GM 74AUP2G14GW
Text: 74AUP2G14 Low-power dual Schmitt trigger inverter Rev. 3 — 22 July 2010 Product data sheet 1. General description The 74AUP2G14 provides two inverting buffers with Schmitt trigger action which accept standard input signals. They are capable of transforming slowly changing input signals
|
Original
|
74AUP2G14
74AUP2G14
74AUP2G14GF
74AUP2G14GM
74AUP2G14GW
|
PDF
|
74AUP1G58
Abstract: 74AUP1G58GF 74AUP1G58GM
Text: 74AUP1G58 Low-power configurable multiple function gate Rev. 4 — 11 October 2010 Product data sheet 1. General description The 74AUP1G58 provides configurable multiple functions. The output state is determined by eight patterns of 3-bit input. The user can choose the logic functions AND, OR, NAND,
|
Original
|
74AUP1G58
74AUP1G58
74AUP1G58GF
74AUP1G58GM
|
PDF
|
74AUP1G14
Abstract: 74AUP1G14GF 74AUP1G14GM 74AUP1G14GW MO-203
Text: 74AUP1G14 Low-power Schmitt trigger inverter Rev. 4 — 13 July 2010 Product data sheet 1. General description The 74AUP1G14 provides a single inverting Schmitt trigger which accepts standard input signals. It is capable of transforming slowly changing input signals into sharply defined,
|
Original
|
74AUP1G14
74AUP1G14
74AUP1G14GF
74AUP1G14GM
74AUP1G14GW
MO-203
|
PDF
|
74LVC1G58
Abstract: 74LVC1G58GF 74LVC1G58GM 74LVC1G58GV 74LVC1G58GW
Text: 74LVC1G58 Low-power configurable multiple function gate Rev. 05 — 15 October 2010 Product data sheet 1. General description The 74LVC1G58 provides configurable multiple functions. The output state is determined by eight patterns of 3-bit input. The user can choose the logic functions AND, OR, NAND,
|
Original
|
74LVC1G58
74LVC1G58
74LVC1G58GF
74LVC1G58GM
74LVC1G58GV
74LVC1G58GW
|
PDF
|
|
|
74AUP1G57
Abstract: 74AUP1G57GF 74AUP1G57GM 74AUP1G57GW JESD22-A114-C transistor VT 209 M CDM 12.6 Philips
Text: 74AUP1G57 Low-power configurable multiple function gate Rev. 01. — 16 January 2006 Preliminary data sheet 1. General description The 74AUP1G57 is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families.
|
Original
|
74AUP1G57
74AUP1G57
74AUP1G57GF
74AUP1G57GM
74AUP1G57GW
JESD22-A114-C
transistor VT 209 M
CDM 12.6 Philips
|
PDF
|
74ALVC14
Abstract: 74ALVC14D 74ALVC14PW TSSOP14
Text: INTEGRATED CIRCUITS DATA SHEET 74ALVC14 Hex inverting Schmitt trigger Product specification 2003 Feb 03 Philips Semiconductors Product specification Hex inverting Schmitt trigger 74ALVC14 FEATURES DESCRIPTION • Wide supply voltage range from 1.65 to 3.6 V
|
Original
|
74ALVC14
74ALVC14
JESD8B/JESD36
SCA75
613508/01/pp16
74ALVC14D
74ALVC14PW
TSSOP14
|
PDF
|
74HC574
Abstract: 74HCT574 74LV574 74LV574D 74LV574DB 74LV574N DIP20 JESD22-A114E SO20 MNA800
Text: 74LV574 Octal D-type flip-flop; positive edge-trigger; 3-state Rev. 04 — 14 May 2009 Product data sheet 1. General description The 74LV574 is an octal D-type flip–flop featuring separate D-type inputs for each flip-flop and non-inverting 3-state outputs for bus oriented applications. A clock CP and an output
|
Original
|
74LV574
74LV574
74HC574
74HCT574.
74HCT574
74LV574D
74LV574DB
74LV574N
DIP20
JESD22-A114E
SO20
MNA800
|
PDF
|
74AUP1G58
Abstract: 74AUP1G58GF 74AUP1G58GM JESD22-A114E
Text: 74AUP1G58 Low-power configurable multiple function gate Rev. 03 — 22 June 2009 Product data sheet 1. General description The 74AUP1G58 provides configurable multiple functions. The output state is determined by eight patterns of 3-bit input. The user can choose the logic functions AND, OR, NAND,
|
Original
|
74AUP1G58
74AUP1G58
74AUP1G58GF
74AUP1G58GM
JESD22-A114E
|
PDF
|
Untitled
Abstract: No abstract text available
Text: 74AUP2G14 Low-power dual Schmitt trigger inverter Rev. 4 — 1 December 2011 Product data sheet 1. General description The 74AUP2G14 provides two inverting buffers with Schmitt trigger action which accept standard input signals. They are capable of transforming slowly changing input signals
|
Original
|
74AUP2G14
74AUP2G14
|
PDF
|
Untitled
Abstract: No abstract text available
Text: 74LVC821A 10-bit D-type flip-flop with 5 V tolerant inputs/outputs; positive-edge trigger; 3-state Rev. 4 — 23 November 2012 Product data sheet 1. General description The 74LVC821A is a 10-bit D-type flip-flop featuring separate D-type inputs for each flip-flop and 3-state outputs for bus-oriented applications. A clock input pin CP and an
|
Original
|
74LVC821A
10-bit
74LVC821A
|
PDF
|
74LVC14A-Q100
Abstract: No abstract text available
Text: 74LVC14A-Q100 Hex inverting Schmitt trigger with 5 V tolerant input Rev. 1 — 7 August 2012 Product data sheet 1. General description The 74LVC14A-Q100 provides six inverting buffers with Schmitt trigger input. It is capable of transforming slowly changing input signals into sharply defined, jitter-free output
|
Original
|
74LVC14A-Q100
74LVC14A-Q100
74LVC14A
|
PDF
|
Untitled
Abstract: No abstract text available
Text: 74HC7540; 74HCT7540 Octal Schmitt trigger buffer/line driver; 3-state; inverting Rev. 3 — 27 August 2012 Product data sheet 1. General description The 74HC7540; 74HCT7540 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL LSTTL . It is specified in compliance with JEDEC standard
|
Original
|
74HC7540;
74HCT7540
74HCT7540
74HCT75
HCT7540
|
PDF
|
Untitled
Abstract: No abstract text available
Text: 74AUP1G58 Low-power configurable multiple function gate Rev. 5 — 29 November 2011 Product data sheet 1. General description The 74AUP1G58 provides configurable multiple functions. The output state is determined by eight patterns of 3-bit input. The user can choose the logic functions AND, OR, NAND,
|
Original
|
74AUP1G58
74AUP1G58
|
PDF
|
Untitled
Abstract: No abstract text available
Text: 74LVC1G57 Low-power configurable multiple function gate Rev. 5 — 22 September 2011 Product data sheet 1. General description The 74LVC1G57 provides configurable multiple functions. The output state is determined by eight patterns of 3-bit input. The user can choose the logic functions AND, OR, NAND,
|
Original
|
74LVC1G57
74LVC1G57
|
PDF
|
