xilinx fifo generator 6.2
Abstract: XC2VP70 XAPP763 XAPP609 XC2VP100 XC2VP20 XC2VP30 XC2VP40 xilinx fifo generator timing RXRECCLK
Text: Application Note: Virtex-II Pro R XAPP763 v1.1 November 18, 2004 Local Clocking for MGT RXRECCLK in Virtex-II Pro Devices Author: Matt Dipaolo and Lyman Lewis Summary This application note describes the local clocking resources available in the Virtex-II Pro
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XAPP763
xapp763
xilinx fifo generator 6.2
XC2VP70
XAPP609
XC2VP100
XC2VP20
XC2VP30
XC2VP40
xilinx fifo generator timing
RXRECCLK
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XAPP1014
Abstract: smpte 424m to smpte 274m 3G-SDI serializer XAPP224 DATA RECOVERY 425M SMPTE-305M PCIe BT.656 ML571 vhdl code for multiplexing Tables in dvb-t SONY service manual circuits
Text: Audio/Video Connectivity Solutions for Virtex-5 FPGAs Reference Designs for the Broadcast Industry: Volume 2 XAPP1014 v1.2 November 9, 2009 Xilinx is disclosing this user guide, manual, release note, and/or specification (the "Documentation") to you solely for use in the development
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XAPP1014
XAPP1014
smpte 424m to smpte 274m
3G-SDI serializer
XAPP224 DATA RECOVERY
425M
SMPTE-305M
PCIe BT.656
ML571
vhdl code for multiplexing Tables in dvb-t
SONY service manual circuits
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XQ5VLX110
Abstract: XQ5VLX330T SX95T DS714 XQ5VFX130T ROCKETIO VIRTEX-5 LX110 UG190 UG191 UG195
Text: 74 Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics DS714 v2.0 December 17, 2009 Product Specification Virtex-5Q FPGA Electrical Characteristics Virtex -5Q FPGAs are available in -2 and -1 speed grades, with -2 having the highest performance. Virtex-5Q FPGA
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DS714
DS174,
UG190,
UG191,
UG192,
UG193,
UG194,
UG195,
UG196,
XQ5VLX110
XQ5VLX330T
SX95T
DS714
XQ5VFX130T
ROCKETIO
VIRTEX-5 LX110
UG190
UG191
UG195
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UG366
Abstract: XC6VLX75T-FF784 aurora GTX XC6VLX240T-FF1759 verilog code of prbs pattern generator XC6VLX130T-FF784 XC6VSX475T-FF XC6VLX240T-FF784 XC6VLX130T FF1156
Text: Virtex-6 FPGA GTX Transceivers User Guide UG366 v2.2 February 23, 2010 Xilinx is disclosing this user guide, manual, release note, and/or specification (the "Documentation") to you solely for use in the development of designs to operate with Xilinx hardware devices. You may not reproduce, distribute, republish, download, display, post, or transmit the
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UG366
UG366
XC6VLX75T-FF784
aurora GTX
XC6VLX240T-FF1759
verilog code of prbs pattern generator
XC6VLX130T-FF784
XC6VSX475T-FF
XC6VLX240T-FF784
XC6VLX130T
FF1156
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UG366
Abstract: LX760
Text: Virtex-6 FPGA Data Sheet: DC and Switching Characteristics DS152 v3.5 May 17, 2013 Product Specification Virtex-6 FPGA Electrical Characteristics Virtex -6 FPGAs are available in -3, -2, -1, and -1L speed grades, with -3 having the highest performance. Virtex-6 FPGA
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DS152
UG366
LX760
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CEI11
Abstract: PRBS11 UG371 XC6VHX255T-FF1155 FPGA Virtex 6 Ethernet h8440 PRBS31 DSP48E1 FF1155 FF1923
Text: Virtex-6 FPGA GTH Transceivers User Guide UG371 v2.0 February 16, 2010 Xilinx is disclosing this user guide, manual, release note, and/or specification (the “Documentation”) to you solely for use in the development of designs to operate with Xilinx hardware devices. You may not reproduce, distribute, republish, download, display, post, or
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UG371
CEI11
PRBS11
UG371
XC6VHX255T-FF1155
FPGA Virtex 6 Ethernet
h8440
PRBS31
DSP48E1
FF1155
FF1923
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verilog code for fibre channel
Abstract: DS518 RXRECCLK PPC405 xilinx 9.1i verilog code fc 2 vhdl code for frame synchronization xilinx logicore fifo generator vhdl code for loop verilog code for frame synchronization
Text: Fibre Channel Arbitrated Loop v2.2 DS518 August 8, 2007 Product Specification Introduction LogiCORE Facts The LogiCORE Fibre Channel Arbitrated Loop FC-AL core provides a flexible, fully verified solution for use in any FC-AL port design. The core handles all link initialization and loop arbitration functions and includes credit
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DS518
verilog code for fibre channel
RXRECCLK
PPC405
xilinx 9.1i
verilog code fc 2
vhdl code for frame synchronization
xilinx logicore fifo generator
vhdl code for loop
verilog code for frame synchronization
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XQR5VFX130-CF1752
Abstract: XQR5VFX
Text: Radiation-Hardened, Space-Grade Virtex-5QV FPGA Data Sheet: DC and Switching Characteristics DS692 v1.2 July 24, 2013 Product Specification Virtex-5QV FPGA Electrical Characteristics Radiation-hardened Virtex -5QV FPGAs are available in the -1 speed grade only. Virtex-5QV FPGA DC and AC
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DS692
DS192,
UG520,
UG190,
UG191,
XQR5VFX130-CF1752
XQR5VFX
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Untitled
Abstract: No abstract text available
Text: ` Virtex-II Pro Platform FPGAs: Introduction and Overview R DS083-1 v2.4.1 March 24, 2003 Advance Product Specification Summary of Virtex-II Pro Features • • High-Performance Platform FPGA Solution, Including - Up to twenty-four RocketIO™ embedded
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DS083-1
18-bit
FF1148)
FF1517)
FF1696)
DS083-4
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Untitled
Abstract: No abstract text available
Text: 89 Spartan-6 FPGA Data Sheet: DC and Switching Characteristics Product Specification DS162 v3.0 October 17, 2011 Spartan-6 FPGA Electrical Characteristics Spartan -6 LX and LXT FPGAs are available in various speed grades, with -3 having the highest performance. The DC and
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DS162
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RX-2C G
Abstract: tx2c transmitter TX 2E 1240 picosecond tx-2b equivalent Gigabyte 848 TX-2B RX-2B ROSENBERGER RX_2B XENPAK70
Text: Virtex-4 RocketIO Multi-Gigabit Transceiver User Guide UG076 v4.1 November 2, 2008 R R Xilinx is disclosing this user guide, manual, release note, and/or specification (the "Documentation") to you solely for use in the development of designs to operate with Xilinx hardware devices. You may not reproduce, distribute, republish, download, display, post, or transmit the
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UG076
8B/10B
RX-2C G
tx2c transmitter
TX 2E
1240 picosecond
tx-2b equivalent
Gigabyte 848
TX-2B RX-2B
ROSENBERGER
RX_2B
XENPAK70
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CVPD-024
Abstract: verilog DPLL XAPP854 AD5320 XAPP514 ROCKETIO X854 x8540 VERILOG Digitally Controlled Oscillator verilog code for phase detector
Text: Application Note: Virtex-4 FPGAs R XAPP854 v1.0 October 10, 2006 Digital Phase-Locked Loop (DPLL) Reference Design Author: Justin Gaither Summary Many applications require a clock signal to be synchronous, phase-locked, or derived from another signal, such as a data signal or another clock. This type of clock circuit is important in
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XAPP854
UG024,
UG029,
XAPP514,
CVPD-024
verilog DPLL
XAPP854
AD5320
XAPP514
ROCKETIO
X854
x8540
VERILOG Digitally Controlled Oscillator
verilog code for phase detector
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vhdl code for deserializer
Abstract: XAPP670 RocketIO ML321 RXRECCLK verilog code for fibre channel vhdl code for DCM
Text: Application Note: Virtex-II Pro Family R XAPP670 v1.0 June 10, 2003 Summary Minimizing Receiver Elastic Buffer Delay in the Virtex-II Pro RocketIO Transceiver Author: Jeremy Kowalczyk This application note describes a design that reduces latency through the receive elastic buffer
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XAPP670
ML321
8B/10B
10-bit,
20-bit,
40-bit
8B/10B
com/pub/applications/xapp/xapp670
vhdl code for deserializer
XAPP670
RocketIO
ML321
RXRECCLK
verilog code for fibre channel
vhdl code for DCM
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MP21608S221A
Abstract: UG198 FERRITE-220 GTX tile oversampling recovered clock ROSENBERGER verilog code for linear interpolation filter aurora GTX BLM15HB221SN1 gearbox rev maxim DVB
Text: Virtex-5 FPGA RocketIO GTX Transceiver User Guide UG198 v2.1 November 17, 2008 R R Xilinx is disclosing this user guide, manual, release note, and/or specification (the "Documentation") to you solely for use in the development of designs to operate with Xilinx hardware devices. You may not reproduce, distribute, republish, download, display, post, or transmit the
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UG198
MP21608S221A
UG198
FERRITE-220
GTX tile oversampling recovered clock
ROSENBERGER
verilog code for linear interpolation filter
aurora GTX
BLM15HB221SN1
gearbox rev
maxim DVB
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ug196
Abstract: johnson tiles GTX tile oversampling recovered clock XC5VLX30T-FF323 aurora GTX ROSENBERGER XC5VSX50TFF665 2F-15 UCF virtex-4 BLM15HB221SN1
Text: Virtex-5 FPGA RocketIO GTP Transceiver User Guide UG196 v2.0 June 10, 2009 Xilinx is disclosing this user guide, manual, release note, and/or specification (the "Documentation") to you solely for use in the development of designs to operate with Xilinx hardware devices. You may not reproduce, distribute, republish, download, display, post, or transmit the
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UG196
ug196
johnson tiles
GTX tile oversampling recovered clock
XC5VLX30T-FF323
aurora GTX
ROSENBERGER
XC5VSX50TFF665
2F-15
UCF virtex-4
BLM15HB221SN1
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XAPP572
Abstract: XAPP684 prbs pattern generator RXRECCLK E0000 XC2VP20
Text: Application Note: Virtex-II Pro Family R XAPP572 v1.0 November 18, 2004 Summary A 3/4/5/6X Oversampling Circuit for 200 Mb/s to 1000 Mb/s Serial Interfaces Author: Jerry Chuang High-speed Serializer/Deserializer (SERDES) devices (1 Gb/s and higher) are often analogbased and tuned for a particular frequency range. If a design requires using the SERDES for
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XAPP572
XAPP684,
XAPP572
XAPP684
prbs pattern generator
RXRECCLK
E0000
XC2VP20
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Untitled
Abstract: No abstract text available
Text: Virtex-II Pro Platform FPGAs: Introduction and Overview R DS083-1 v2.3 November 20, 2002 Advance Product Specification Summary of Virtex-II Pro Features • • High-Performance Platform FPGA Solution, Including - Up to twenty-four RocketIO™ embedded
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DS083-1
18-bit
DS083-4
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c405d
Abstract: No abstract text available
Text: R Chapter 1 Timing Models Summary The following topics are covered in this chapter: • Processor Block Timing Model • Rocket I/O Timing Model • CLB / Slice Timing Model • Block SelectRAM Timing Model • Embedded Multiplier Timing Model • IOB Timing Model
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UG012
c405d
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4x4 unsigned multiplier VERILOG coding
Abstract: vhdl code for lvds driver 32x32 multiplier verilog code MULT18X18 12v relay interface with cpld in vhdl verilog/verilog code for lvds driver 80C31 instruction set vhdl code for 18x18 unSIGNED MULTIPLIER vhdl pulse interval encoder book national semiconductor
Text: R Chapter 2 Design Considerations Summary This chapter covers the following topics: • • • • • • • • • • • • • • • • • Rocket I/O Transceiver Processor Block Global Clock Networks Digital Clock Managers DCMs Block SelectRAM Memory
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UG012
4x4 unsigned multiplier VERILOG coding
vhdl code for lvds driver
32x32 multiplier verilog code
MULT18X18
12v relay interface with cpld in vhdl
verilog/verilog code for lvds driver
80C31 instruction set
vhdl code for 18x18 unSIGNED MULTIPLIER
vhdl pulse interval encoder
book national semiconductor
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405D5
Abstract: basic block diagram of bit slice processors carry look ahead adder XAPP290 dci -dc inverter repeater 10g passive transmitter circuit in GPR 405D4 LVCMOS33 PPC405
Text: 48 Virtex-II Pro Platform FPGAs: Functional Description R DS083-2 v3.1.1 March 9, 2004 Product Specification Virtex-II Pro Array Functional Description CLB CLB All of the documents above, as well as a complete listing and description of Xilinx-developed Intellectual Property
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DS083-2
405D5
basic block diagram of bit slice processors
carry look ahead adder
XAPP290
dci -dc inverter
repeater 10g passive
transmitter circuit in GPR
405D4
LVCMOS33
PPC405
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AB38R
Abstract: tag l9 225 400 XC2VP20 XC2VP50
Text: Virtex-II Pro Platform FPGAs: Introduction and Overview R DS083-1 v2.0 June 13, 2002 Advance Product Specification Summary of Virtex-II Pro Features • • High-performance Platform FPGA solution including - Up to twenty-four Rocket I/O™ embedded multi-gigabit transceiver blocks (based on
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DS083-1
18-bit
and255-7778
DS083-4
AB38R
tag l9 225 400
XC2VP20
XC2VP50
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Untitled
Abstract: No abstract text available
Text: Virtex-6 FPGA Data Sheet: DC and Switching Characteristics DS152 v3.6 March 18, 2014 Product Specification Virtex-6 FPGA Electrical Characteristics Virtex -6 FPGAs are available in -3, -2, -1, and -1L speed grades, with -3 having the highest performance. Virtex-6 FPGA
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xc2vp1257
Abstract: 2VP125 XC2VP70 FF1704 FG456 2vp12 XC2VP50
Text: Virtex-II Pro Platform FPGAs: Introduction and Overview R DS083-1 v2.2 September 27, 2002 Advance Product Specification Summary of Virtex-II Pro Features • • High-Performance Platform FPGA Solution, Including - Up to twenty-four Rocket I/O™ embedded
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18-bit
XC2VP30,
FF1152
DS083-4
xc2vp1257
2VP125
XC2VP70 FF1704
FG456
2vp12
XC2VP50
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XC6SLX45
Abstract: XC6SLX150 Xilinx Spartan-6 LX9 XC6SLX75 xc6slx150t XC6SLX25CSG324 XC6SLX4 xc6slx16 XC6SLX4 2 CSG225 I XC6SLX25-CSG324
Text: 80 Spartan-6 FPGA Data Sheet: DC and Switching Characteristics DS162 v2.1 May 20, 2011 Preliminary Product Specification Spartan-6 FPGA Electrical Characteristics Spartan -6 LX FPGAs are available in -3, -3N, -2, and -1L speed grades, with -3 having the highest performance.
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DS162
XC6SLX45
XC6SLX150
Xilinx Spartan-6 LX9
XC6SLX75
xc6slx150t
XC6SLX25CSG324
XC6SLX4
xc6slx16
XC6SLX4 2 CSG225 I
XC6SLX25-CSG324
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