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Abstract: No abstract text available
Text: Package outline XSON6: extremely thin small outline package; no leads; 6 terminals; body 0.9 x 1.0 x 0.35 mm 1 SOT1115 b 3 2 4x (2) L L1 e 6 5 4 e1 e1 (6×)(2) A1 A D E terminal 1 index area 0.5 Dimensions Unit mm 1 mm scale A(1) A1 b D E e max 0.35 0.04 0.20 0.95 1.05
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OT1115
sot1115
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Untitled
Abstract: No abstract text available
Text: SOT1115 Reversed product orientation 12NC ending 132. Rev. 02 — 27 July 2011 Packing information 1. Packing method Fig. 1 Package version 12NC ending Reel dimensions d x w mm SPQ/PQ (pcs) Reels per box Outer box dimensions l x w x h (mm) SOT1115 132 180 x 8
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OT1115
OT1115
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74AVCH1T45
Abstract: No abstract text available
Text: 74AVCH1T45 Dual-supply voltage level translator/transceiver; 3-state Rev. 4 — 3 August 2012 Product data sheet 1. General description The 74AVCH1T45 is a single bit, dual supply transceiver that enables bidirectional level translation. It features two 1-bit input-output ports A and B , a direction control input (DIR)
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74AVCH1T45
74AVCH1T45
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Abstract: No abstract text available
Text: 74LVC1G14 Single Schmitt-trigger inverter Rev. 12 — 6 August 2012 Product data sheet 1. General description The 74LVC1G14 provides the inverting buffer function with Schmitt-trigger input. It is capable of transforming slowly changing input signals into sharply defined, jitter-free
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74LVC1G14
74LVC1G14
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application note tssop5 nxp
Abstract: No abstract text available
Text: 74LVC1G06 Inverter with open-drain output Rev. 10 — 29 June 2012 Product data sheet 1. General description The 74LVC1G06 provides the inverting buffer. Input can be driven from either 3.3 V or 5 V devices. These features allow the use of these devices in a mixed 3.3 V and 5 V environment.
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74LVC1G06
74LVC1G06
application note tssop5 nxp
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Abstract: No abstract text available
Text: 74LVC1G08 Single 2-input AND gate Rev. 9 — 9 December 2011 Product Specification 1. General description The 74LVC1G08 provides one 2-input AND function. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V applications.
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74LVC1G08
74LVC1G08
771-LVC1G08GWDG125
74LVC1G08GW/DG
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marking VU SOT363
Abstract: No abstract text available
Text: 74LVC1G11 Single 3-input AND gate Rev. 7 — 4 July 2012 Product data sheet 1. General description The 74LVC1G11 provides a single 3-input AND gate. The input can be driven from either 3.3 V or 5 V devices. This feature allows the use of this device in a mixed 3.3 V and 5 V environment.
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74LVC1G11
74LVC1G11
marking VU SOT363
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Abstract: No abstract text available
Text: 74LVC1GU04 Inverter Rev. 11 — 2 July 2012 Product data sheet 1. General description The 74LVC1GU04 provides the inverting single state unbuffered function. The input can be driven from either 3.3 V or 5 V devices. This feature allows the use of this device in a mixed 3.3 V and 5 V environment.
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74LVC1GU04
74LVC1GU04
JESD22-A114F
JESD22-A115-A
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74AUP1G00GW
Abstract: 74AUP1G00 74AUP1G00GF 74AUP1G00GM
Text: 74AUP1G00 Low-power 2-input NAND gate Rev. 3 — 7 October 2010 Product data sheet 1. General description The 74AUP1G00 provides the single 2-input NAND function. Schmitt-trigger action at all inputs makes the circuit tolerant to slower input rise and fall
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74AUP1G00
74AUP1G00
74AUP1G00GW
74AUP1G00GF
74AUP1G00GM
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74LVC1G332
Abstract: 74LVC1G332GF 74LVC1G332GM 74LVC1G332GV 74LVC1G332GW
Text: 74LVC1G332 Single 3-input OR gate Rev. 3 — 26 October 2010 Product data sheet 1. General description The 74LVC1G332 provides one 3-input OR function. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V applications.
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74LVC1G332
74LVC1G332
74LVC1G332GF
74LVC1G332GM
74LVC1G332GV
74LVC1G332GW
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74LVC1G126
Abstract: 74LVC1G126GF 74LVC1G126GM 74LVC1G126GV 74LVC1G126GW
Text: 74LVC1G126 Bus buffer/line driver; 3-state Rev. 9 — 25 August 2010 Product data sheet 1. General description The 74LVC1G126 provides one non-inverting buffer/line driver with 3-state output. The 3-state output is controlled by the output enable input OE . A LOW-level at pin OE
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74LVC1G126
74LVC1G126
74LVC1G126GF
74LVC1G126GM
74LVC1G126GV
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74LVC1G125GW
Abstract: 74LVC1G125 74LVC1G125GF 74LVC1G125GM 74LVC1G125GV VM MARKING CODE SOT353
Text: 74LVC1G125 Bus buffer/line driver; 3-state Rev. 8 — 24 August 2010 Product data sheet 1. General description The 74LVC1G125 provides one non-inverting buffer/line driver with 3-state output. The 3-state output is controlled by the output enable input OE . A HIGH-level at pin OE
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74LVC1G125
74LVC1G125
74LVC1G125GW
74LVC1G125GF
74LVC1G125GM
74LVC1G125GV
VM MARKING CODE SOT353
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74AUP1G34
Abstract: 74AUP1G34GF 74AUP1G34GM 74AUP1G34GW
Text: 74AUP1G34 Low-power buffer Rev. 4 — 14 July 2010 Product data sheet 1. General description The 74AUP1G34 provides a low-power, low-voltage single buffer. Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 0.8 V to 3.6 V.
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74AUP1G34
74AUP1G34
74AUP1G34GF
74AUP1G34GM
74AUP1G34GW
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74AUP1T34GF
Abstract: 74AUP1T34GM MO-203
Text: 74AUP1T34 Low-power dual supply translating buffer Rev. 2 — 19 August 2010 Product data sheet 1. General description The 74AUP1T34 provides a single buffer with two separate supply voltages. Input A is designed to track VCC A . Output Y is designed to track VCC(Y). Both, VCC(A) and VCC(Y)
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74AUP1T34
74AUP1T34
74AUP1T34GF
74AUP1T34GM
MO-203
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JESD22-A114E
Abstract: No abstract text available
Text: 74AUP1G09 Low-power 2-input AND gate with open-drain Rev. 2 — 9 July 2010 Product data sheet 1. General description The 74AUP1G09 provides the single 2-input AND gate with an open-drain output. The output of the device is an open-drain and can be connected to other open-drain outputs to
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74AUP1G09
74AUP1G09
JESD22-A114E
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74LVC1G57
Abstract: 74LVC1G57GF 74LVC1G57GM 74LVC1G57GV 74LVC1G57GW
Text: 74LVC1G57 Low-power configurable multiple function gate Rev. 4 — 15 October 2010 Product data sheet 1. General description The 74LVC1G57 provides configurable multiple functions. The output state is determined by eight patterns of 3-bit input. The user can choose the logic functions AND, OR, NAND,
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74LVC1G57
74LVC1G57
74LVC1G57GF
74LVC1G57GM
74LVC1G57GV
74LVC1G57GW
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74LVC1G157
Abstract: 74LVC1G157GF 74LVC1G157GM 74LVC1G157GV 74LVC1G157GW
Text: 74LVC1G157 Single 2-input multiplexer Rev. 4 — 28 October 2010 Product data sheet 1. General description The 74LVC1G157 is a single 2-input multiplexer which select data from two data inputs I0 and I1 under control of a common data select input (S). The state of the common data
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74LVC1G157
74LVC1G157
74LVC1G157GF
74LVC1G157GM
74LVC1G157GV
74LVC1G157GW
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74AUP1G0832
Abstract: 74AUP1G0832GF 74AUP1G0832GM 74AUP1G0832GW
Text: 74AUP1G0832 Low-power 3-input AND-OR gate Rev. 3 — 5 October 2010 Product data sheet 1. General description The 74AUP1G0832 provides the Boolean function: Y = A x B + C. The user can choose the logic functions OR, AND and AND-OR. All inputs can be connected to VCC or GND.
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74AUP1G0832
74AUP1G0832
74AUP1G0832GF
74AUP1G0832GM
74AUP1G0832GW
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74AUP2G14
Abstract: 74AUP2G14GF 74AUP2G14GM 74AUP2G14GW
Text: 74AUP2G14 Low-power dual Schmitt trigger inverter Rev. 3 — 22 July 2010 Product data sheet 1. General description The 74AUP2G14 provides two inverting buffers with Schmitt trigger action which accept standard input signals. They are capable of transforming slowly changing input signals
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74AUP2G14
74AUP2G14
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3-input orgate
Abstract: SOT-120 74AUP1G332 74AUP1G332GF 74AUP1G332GM 74AUP1G332GW
Text: 74AUP1G332 Low-power 3-input OR-gate Rev. 3 — 7 October 2010 Product data sheet 1. General description The 74AUP1G332 provides a single 3-input OR gate. Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 0.8 V to 3.6 V.
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74AUP1G332
74AUP1G332
3-input orgate
SOT-120
74AUP1G332GF
74AUP1G332GM
74AUP1G332GW
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Abstract: No abstract text available
Text: 74LVC1G19 1-of-2 decoder/demultiplexer Rev. 7 — 10 September 2014 Product data sheet 1. General description The 74LVC1G19 is a 1-of-2 decoder/demultiplexer with a common output enable. This device buffers the data on input A and passes it to the outputs 1Y true and 2Y
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74LVC1G19
74LVC1G19
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Untitled
Abstract: No abstract text available
Text: 74AXP1G58 Low-power configurable multiple function gate Rev. 2 — 24 July 2014 Product data sheet 1. General description The 74AXP1G58 is a configurable multiple function gate with Schmitt-trigger inputs. The device can be configured as any of the following logic functions AND, OR, NAND, NOR,
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74AXP1G58
74AXP1G58
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74LVC1G04
Abstract: 74LVC1G04GF 74LVC1G04GM 74LVC1G04GV 74LVC1G04GW
Text: 74LVC1G04 Single inverter Rev. 9 — 26 October 2010 Product data sheet 1. General description The 74LVC1G04 provides one inverting buffer. Input can be driven from either 3.3 V or 5 V devices. These features allow the use of these devices in a mixed 3.3 V and 5 V environment.
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74LVC1G04
74LVC1G04
74LVC1G04GF
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74LVC1G04GV
74LVC1G04GW
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74LVC1G384
Abstract: 74LVC1G384GF 74LVC1G384GM 74LVC1G384GV 74LVC1G384GW
Text: 74LVC1G384 Bilateral switch Rev. 3 — 3 November 2010 Product data sheet 1. General description The 74LVC1G384 provides one single pole, single throw analog switch function. It has two input/output terminals Y and Z and an active LOW enable input pin (E). When pin E
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74LVC1G384
74LVC1G384
JESD22-A114F
JESD22-A115-A
74LVC1G384GF
74LVC1G384GM
74LVC1G384GV
74LVC1G384GW
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