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    74SSTVF16857PAG Renesas Electronics Corporation 14-Bit Registered Buffer with SSTL I/O Visit Renesas Electronics Corporation
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    74SSTV16857PAG8 Renesas Electronics Corporation 14-Bit Registered Buffer with SSTL I/O Visit Renesas Electronics Corporation
    74SSTVF16857PAG8 Renesas Electronics Corporation 14-Bit Registered Buffer with SSTL I/O Visit Renesas Electronics Corporation
    74SSTVN16859CPAG8 Renesas Electronics Corporation 13-Bit to 26-Bit Registered Buffer with SSTL I/O Visit Renesas Electronics Corporation
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    Rochester Electronics LLC 5LN01SS-TL-H

    MOSFET N-CH 50V 100MA 3SSFP
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    MOSFET N-CH 30V 150MA SC81
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    5LN01 - N-CHANNEL SILICON MOSFET
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    Flip Electronics 15C01SS-TL-E

    TRANS NPN 15V 0.6A 3SSFP
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    SSTL Datasheets (18)

    Part ECAD Model Manufacturer Description Curated Datasheet Type PDF
    SSTL16857 NXP Semiconductors Memory interfaces; Support logic for memory modules and other memory subsystems Original PDF
    SSTL16857 Philips Semiconductors 14-bit SSTL_2 registered driver with differential clock inputs Original PDF
    SSTL16857DGG Philips Semiconductors 14 Bit SSTL-2 Registered Driver with Differential Clock Inputs Original PDF
    SSTL16857DGG Philips Semiconductors 14 Bit SSTL-2 Registered Driver with Differential Clock Inputs Scan PDF
    SSTL16857DGG Philips Semiconductors 14-bit SSTL_2 Registered Driver with Differential Clock Inputs Scan PDF
    SSTL16857DGG,512 NXP Semiconductors 14-bit SSTL_2 registered driver with differential clock inputs - Application: DDR SDRAM register ; Hold time (CLK-DATA): 0.5 ns; Inputs: 14 x SSTL-2 ; Operating frequency: 200 MHz; Operating temperature: 0~+70 Cel; Other features: master reset ; Outputs: 14 x SSTL-2 ; Propagation delay: 1.8 ns; Set-up time (DATA-CLK): 0.8 ns; Supply voltage: 2.53.3 V; Package: SOT362-1 (TSSOP48); Container: Tube Dry Pack Original PDF
    SSTL16857DGG,518 NXP Semiconductors 14-bit SSTL_2 registered driver with differential clock inputs - Application: DDR SDRAM register ; Hold time (CLK-DATA): 0.5 ns; Inputs: 14 x SSTL-2 ; Operating frequency: 200 MHz; Operating temperature: 0~+70 Cel; Other features: master reset ; Outputs: 14 x SSTL-2 ; Propagation delay: 1.8 ns; Set-up time (DATA-CLK): 0.8 ns; Supply voltage: 2.53.3 V; Package: SOT362-1 (TSSOP48); Container: Reel Dry Pack, SMD, 13" Original PDF
    SSTL16857DG-T Philips Semiconductors 14-bit SSTL_2 registered driver with differential clock inputs Original PDF
    SSTL16877 NXP Semiconductors Memory interfaces; Support logic for memory modules and other memory subsystems Original PDF
    SSTL16877 Philips Semiconductors 14-bit SSTL_2 registered driver with differential clock inputs Original PDF
    SSTL16877 Philips Semiconductors 14-bit SSTL_2 registered driver with differential clock inputs Original PDF
    SSTL16877DG NXP Semiconductors 14-bit SSTL_2 registered driver with differential clock inputs - Application: DDR SDRAM register ; Hold time (CLK-DATA): 1.2 ns; Inputs: 14 x SSTL-2 ; Operating frequency: 200 MHz; Operating temperature: 0~+70 Cel; Other features: master reset ; Outputs: 14 x SSTL-2 ; Propagation delay: 2.4 ns; Set-up time (DATA-CLK): 0.2 ns; Supply voltage: 2.5 V Original PDF
    SSTL16877DGG Philips Semiconductors 14 Bit SSTL_2 Registered Driver with Differential Clock Inputs Original PDF
    SSTL16877DGG Philips Semiconductors 14-bit SSTL_2 registered driver with differential clock inputs Original PDF
    SSTL16877DGG,512 Philips Semiconductors Logic - Universal Bus Functions, Integrated Circuits (ICs), IC REG DRIVER 14BIT 48TSSOP Original PDF
    SSTL16877DGG,518 Philips Semiconductors Logic - Universal Bus Functions, Integrated Circuits (ICs), IC REG DRIVER 14BIT 48TSSOP Original PDF
    SSTL16877DGG/G Philips Semiconductors SSTL16877, 14-bit SSTL_2 registered driver with differential clock inputs Original PDF
    SSTL16877DGG-T NXP Semiconductors 14-bit SSTL_2 registered driver with differential clock inputs - Application: DDR SDRAM register ; Hold time (CLK-DATA): 1.2 ns; Inputs: 14 x SSTL-2 ; Operating frequency: 200 MHz; Operating temperature: 0~+70 Cel; Other features: master reset ; Outputs: 14 x SSTL-2 ; Propagation delay: 2.4 ns; Set-up time (DATA-CLK): 0.2 ns; Supply voltage: 2.5 V Original PDF

    SSTL Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    Untitled

    Abstract: No abstract text available
    Text: SN74CBTLV3857 LOW-VOLTAGE 10-BIT FET BUS SWITCH WITH INTERNAL PULLDOWN RESISTORS SCDS085C – OCTOBER 1998 – REVISED MAY 2000 D D D D D D D D DBQ, DGV, DW, OR PW PACKAGE TOP VIEW Enable Signal Is SSTL_2 Compatible Flow-Through Architecture Optimizes PCB


    Original     		PDF SN74CBTLV3857 10-BIT SCDS085C

    Untitled

    Abstract: No abstract text available
    Text: Preliminary Datasheet 1.5A DDR TERMINATION REGULATOR AP2301 General Description Features The AP2301 linear regulator is designed to meet the JEDEC specification SSTL-2 and SSTL-18 for termination of DDR-SDRAM. The regulator can sink or source up to 1.5A current continuously, offers enough


    Original     		PDF AP2301 AP2301 SSTL-18 25VTT)

    Untitled

    Abstract: No abstract text available
    Text: SN74SSTV16857 14ĆBIT REGISTERED BUFFER WITH SSTL_2 INPUTS AND OUTPUTS SCES344E – DECEMBER 2000 – REVISED NOVEMBER 2002 D Member of the Texas Instruments D D D D D D D D DGG PACKAGE TOP VIEW Widebus Family Supports SSTL_2 Data Inputs Outputs Meet SSTL_2 Class II


    Original     		PDF SN74SSTV16857 14BIT SCES344E 000-V A114-A) A115-A) 14-bit

    A115-A

    Abstract: C101 SN74SSTU32864D SN74SSTU32864DGKER TOP-SIDE MARKING H2 SU864D
    Text: SN74SSTU32864D 25-BIT CONFIGURABLE REGISTERED BUFFER WITH SSTL_18 INPUTS AND OUTPUTS www.ti.com SCES623A – FEBRUARY 2005 – REVISED APRIL 2005 FEATURES • • • • • • Member of the Texas Instruments Widebus+ Family Pinout Optimizes DDR2 DIMM PCB Layout


    Original     		PDF SN74SSTU32864D 25-BIT SCES623A 14-Bit A115-A C101 SN74SSTU32864D SN74SSTU32864DGKER TOP-SIDE MARKING H2 SU864D

    A115-A

    Abstract: C101 SN74SSTV32877 SN74SSTV32877GKER
    Text: SN74SSTV32877 26-BIT REGISTERED BUFFER WITH SSTL_2 INPUTS AND OUTPUTS SCES378B – OCTOBER 2001 – REVISED MAY 2002 D D D D D D Member of the Texas Instruments Widebus+ Family Supports SSTL_2 Data Inputs Outputs Meet SSTL_2 Class II Specifications Differential Clock Inputs CLK and CLK


    Original     		PDF SN74SSTV32877 26-BIT SCES378B 000-V A114-A) A115-A) A115-A C101 SN74SSTV32877 SN74SSTV32877GKER

    Untitled

    Abstract: No abstract text available
    Text: LP2998/LP2998-Q1 www.ti.com SNVS521J – DECEMBER 2007 – REVISED DECEMBER 2013 LP2998/LP2998-Q1 DDR-I and DDR-II Termination Regulator Check for Samples: LP2998/LP2998-Q1 FEATURES DESCRIPTION • The LP2998 linear regulator is designed to meet JEDEC SSTL-2 and JEDEC SSTL-18 specifications


    Original     		PDF LP2998/LP2998-Q1 SNVS521J LP2998/LP2998-Q1 LP2998 SSTL-18

    SN74CBTLV3857

    Abstract: SN74CBTLV3857DBQR SN74CBTLV3857DGVR SN74CBTLV3857DW SN74CBTLV3857DWR SN74CBTLV3857PWR
    Text: SN74CBTLV3857 LOW-VOLTAGE 10-BIT FET BUS SWITCH WITH INTERNAL PULLDOWN RESISTORS SCDS085D – OCTOBER 1998 – REVISED MARCH 2001 D D D D D D D DBQ, DGV, DW, OR PW PACKAGE TOP VIEW Enable Signal Is SSTL_2 Compatible Flow-Through Architecture Optimizes PCB


    Original     		PDF SN74CBTLV3857 10-BIT SCDS085D SN74CBTLV3857 SN74CBTLV3857DBQR SN74CBTLV3857DGVR SN74CBTLV3857DW SN74CBTLV3857DWR SN74CBTLV3857PWR

    SN74SSTL16847

    Abstract: No abstract text available
    Text: SSTL16847 20-BIT SSTL_3 INTERFACE BUFFER WITH 3-STATE OUTPUTS SCBS709A – OCTOBER 1997 – REVISED MAY 1998 D D D D D D D DGG PACKAGE TOP VIEW Member of the Texas Instruments Widebus Family Supports SSTL_3 Signal Inputs and Outputs Flow-Through Architecture Optimizes PCB


    Original     		PDF SN74SSTL16847 20-BIT SCBS709A MIL-STD-883, SN74SSTL16847

    D869

    Abstract: marking nb IDT74SSTU32D869
    Text: IDT74SSTU32D869 14-BIT 1:2 REGISTERED BUFFER WITH PARITY COMMERCIAL TEMPERATURE RANGE 14-BIT 1:2 REGISTERED BUFFER WITH PARITY IDT74SSTU32D869 FEATURES: • • • • • • • • 1.8V Operation Designed to drive low impedance nets SSTL_18 style clock and data inputs


    Original     		PDF IDT74SSTU32D869 14-BIT 100mA MIL-STD-883, 200pF, 150-pin 10MHz, D869 marking nb IDT74SSTU32D869

    DTM63614

    Abstract: No abstract text available
    Text: DTM63614 1GB-128M x 72, 184 Pin Registered DDR SDRAM DIMM Performance Range 266MHz/CL=2.5 200MHz/CL=2 Features Description Utilizes 133MHz DDR SDRAM Auto & self refresh capability SSTL_2 compatible inputs and outputs VDD/VDDQ= 2.5V +/- 0.2V MRS cycle, with address key, programs Latency Access


    Original     		PDF DTM63614 1GB-128M 266MHz/CL 200MHz/CL 133MHz 184-pin DTM63614 DTM6361ANCE 100MHz) DQ0-DQ63,

    F-100

    Abstract: ML6553 ML6553CS-1
    Text: www.fairchildsemi.com ML6553 Bus Termination Regulator Features General Description • Can source and sink up to 1A • Generates termination voltages for DDR SDRAM, SSTL_2 SDRAM, SGRAM, or equivalent memories • Generates termination voltages for active termination


    Original     		PDF ML6553 800mA ML6553 DS30001584 F-100 ML6553CS-1

    SSTV16857

    Abstract: No abstract text available
    Text: Preliminary Revised April 2000 SSTV16857 14-Bit Register with SSTL-2 Compatible I/O and Reset Preliminary General Description Features The SSTV16857 is a 14-bit register designed for use with 184 and 232 pin DDR-I memory modules. The device has a differential input clock, SSTL-2 compatible data inputs


    Original     		PDF SSTV16857 14-Bit

    SMD 7014

    Abstract: No abstract text available
    Text: www.fairchildsemi.com ML6554 3A Bus Termination Regulator Features Description • Can source and sink up to 3A, no heat sink required • Integrated Power MOSFETs • Generates termination voltages for DDR SDRAM, SSTL-2 SDRAM, SGRAM, or equivalent memories


    Original     		PDF ML6554 ML6554 DS30006554 SMD 7014

    Q1B-Q13B

    Abstract: SSTV16859
    Text: Revised March 2001 SSTV16859 Dual Output 13-Bit Register with SSTL-2 Compatible I/O and Reset General Description Features The SSTV16859 is a dual output 13-bit register designed for use with 184 and 232 pin DDR-1 memory modules. The device has a differential input clock, SSTL-2 compatible


    Original     		PDF SSTV16859 13-Bit Q1B-Q13B

    857l

    Abstract: SY55857L SY55857LKG SY55857LKGTR SY55857LKI SY55857LKITR SY58021U
    Text: Micrel, Inc. SuperLite SY55857L SuperLite™ 3.3V, 2.5Gbps ANY INPUT-to-LVPECL DUAL TRANSLATOR SY55857L FEATURES • Input accepts virtually all logic standards: • Single-ended: SSTL, TTL, CMOS • Differential: LVDS, HSTL, CML ■ Guaranteed AC parameters over temperature:


    Original     		PDF SY55857L 200ps 400ps 46mW/channel 10-pin SY55857L M9999-082306 857l SY55857LKG SY55857LKGTR SY55857LKI SY55857LKITR SY58021U

    Untitled

    Abstract: No abstract text available
    Text: CBTW28DD14 14-bit bus switch/multiplexer for DDR2/DDR3/DDR4 applications Rev. 6 — 25 July 2014 Product data sheet 1. General description This 14-bit bus switch/multiplexer MUX is designed for 1.5 V or 1.8 V supply voltage operation, POD_12, SSTL_12, SSTL_135, SSTL_15 or SSTL_18 signaling and CMOS


    Original     		PDF CBTW28DD14 14-bit CBTW28DD14

    SPARTAN XC2S50

    Abstract: SPARTAN-II SPARTAN-II xc2s100 pq208 CS144 FG256 PQ208 TQ144 VQ100 XC2S100 XC2S15
    Text: Robust Feature Set • Flexible on-chip memory Distributed and Block Memory • 4 Digital Delay Lock Loops per device Efficient chip level/ board level clock management • Select I/O Technology Interface to all major bus standards HSTL, GTL, SSTL, etc…


    Original     		PDF PQ208 FG256 FG456 SPARTAN XC2S50 SPARTAN-II SPARTAN-II xc2s100 pq208 CS144 FG256 PQ208 TQ144 VQ100 XC2S100 XC2S15

    is46dr32801a-5bbla1

    Abstract: 126-ball IS46DR32801A
    Text: IS43DR32800A, IS43/46DR32801A 8Mx32 256Mb DDR2 DRAM FEATURES • Vdd = 1.8V ±0.1V, Vddq = 1.8V ±0.1V • JEDEC standard 1.8V I/O SSTL_18-compatible • Double data rate interface: two data transfers per clock cycle • Differential data strobe (DQS, DQS)


    Original     		PDF IS43DR32800A, IS43/46DR32801A 8Mx32 256Mb 18-compatible) DDR2-667D IS43DR32801A-3DBLI DDR2-533C IS43DR32801A-37CBLI DDR2-400B is46dr32801a-5bbla1 126-ball IS46DR32801A

    IS43DR83200A

    Abstract: IS43DR16160A-3DBLI datasheet IS43DR16160A-37CBLI IS43DR83200A-37CBLI IS43DR32160A DDR2 x32
    Text: IS43DR83200A IS43/46DR16160A, IS43DR32160A 32Mx8, 16Mx16, 16Mx32 stacked die DDR2 DRAM FEATURES • Vdd = 1.8V ±0.1V, Vddq = 1.8V ±0.1V • JEDEC standard 1.8V I/O (SSTL_18-compatible) • Double data rate interface: two data transfers per clock cycle


    Original     		PDF IS43DR83200A IS43/46DR16160A, IS43DR32160A 32Mx8, 16Mx16, 16Mx32 18-compatible) IS43DR32160A-37CBLI 400Mhz IS43DR32160A-5BBLI IS43DR83200A IS43DR16160A-3DBLI datasheet IS43DR16160A-37CBLI IS43DR83200A-37CBLI IS43DR32160A DDR2 x32

    Untitled

    Abstract: No abstract text available
    Text: SC2595 Integrated Linear DDR Termination Regulator POWER MANAGEMENT Description Features The SC2595 is an integrated linear DDR termination device which provides a complete solution for DDR termination designs while meeting the JEDEC requirements of SSTL-2 specifications for DDR-SDRAM


    Original     		PDF SC2595

    C 151 C

    Abstract: LP2995M
    Text: February 2002 LP2995 DDR Termination Regulator General Description Features The LP2995 regulator is designed to provide a linear solution to meet the JEDEC SSTL-2 and SSTL-3 specifications for termination of DDR-SDRAM. The device contains a high-speed operational amplifier to provide excellent response to load transients. The output stage prevents shoot


    Original     		PDF LP2995 C 151 C LP2995M

    Untitled

    Abstract: No abstract text available
    Text: SSTL16857 14-bit SSTL_2 Registered Buffer HITACHI ADE-205-223B Z Preliminary 3rd. Edition February 1999 Description The SSTL16857 is a 14-bit registered buffer designed for 2.3 V to 3.6 V Vcc operation and LVCMOS reset (RESET) input / SSTL_2 data (D) inputs and CLK input.


    OCR Scan     		PDF HD74SSTL16857 14-bit ADE-205-223B HD74SSTL16857 TTP-48DC

    Untitled

    Abstract: No abstract text available
    Text: HM5425161B Series HM5425801B Series HM5425401B Series 256M SSTL_2 interface DDR SDRAM 143 MHz/133 MHz/125 MHz/100 MHz 4-Mword x 16-bit x 4-bank/8-Mword x 8-bit x 4-bank/ 16-Mword x 4 -bit x 4 -bank HITACHI ADE-203-1077 Z Preliminary Rev. 0.0 Jun. 28, 1999


    OCR Scan     		PDF HM5425161B HM5425801B HM5425401B Hz/133 Hz/125 Hz/100 16-bit 16-Mword ADE-203-1077 HM5425161B,

    Untitled

    Abstract: No abstract text available
    Text: SSTL16837A 20-BIT SSTL 3 INTERFACE UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS S C BS 675G - S E P TE M B E R 1996 - R EVISED S E P TE M B E R 1998 Member of the Texas Instruments Widebus Family DGG PACKAGE TOP VIEW Supports SSTL 3 Signal Inputs and


    OCR Scan     		PDF SN74SSTL16837A 20-BIT