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XAPP186 Abstract: XAPP216 XAPP-186 SelectMAP SRL16 XAPP137 XAPP138 XAPP151 XQVR1000 XQVR300 Text: Application Note: FPGAs R XAPP216 v1.0 June 1, 2000 Correcting Single-Event Upsets Through Virtex Partial Configuration Author: Carl Carmichael Co-authors: Michael Caffrey, Anthony Salazar; Los Alamos National Laboratories Summary This application note describes the use of partial reconfiguration in Virtex series FPGAs for	Original	XAPP216 XAPP138 XQVR300 XQVR600 XQVR1000 32-bit) XAPP186 XAPP216 XAPP-186 SelectMAP SRL16 XAPP137 XAPP151 XQVR1000 XQVR300	PDF
CREME96 Abstract: cots fpga radiation 115641 fpga radiation COTS radiation cots cmos RAM SEU proton XQVR300 Text: Radiation Testing Update, SEU Mitigation, and Availability Analysis of the Virtex FPGA for Space Reconfigurable Computing † Earl Fuller2, Michael Caffrey1, Anthony Salazar1, Carl Carmichael3, Joe Fabula 3 1 Los Alamos National Laboratory 2 Novus Technologies, Inc.	Original	CREME96: XAPP216, CREME96 cots fpga radiation 115641 fpga radiation COTS radiation cots cmos RAM SEU proton XQVR300	PDF
Synplify tmr Abstract: CC16CE vhdl code hamming edac memory vhdl code for a grey-code counter XAPP216 voter CC16RE vhdl coding for error correction and detection algorithms vhdl code hamming RAM EDAC SEU Text: Application Note: Virtex Series R XAPP197 v1.0 November 1, 2001 Triple Module Redundancy Design Techniques for Virtex FPGAs Author: Carl Carmichael Summary Triple Module Redundancy (TMR) combined with Single Event Upset (SEU) correction through partial reconfiguration is a powerful and effective SEU mitigation strategy. This method is only	Original	XAPP197 XAPP216, XAPP216 Synplify tmr CC16CE vhdl code hamming edac memory vhdl code for a grey-code counter voter CC16RE vhdl coding for error correction and detection algorithms vhdl code hamming RAM EDAC SEU	PDF
XAPP987 Abstract: voter XAPP988 XAPP216 RAM SEU fpga radiation CREME96 Upsets XAPP779 XQR2V6000 Text: Application Note: FPGAs Single-Event Upset Mitigation Selection Guide R Author: Brendan Bridgford, Carl Carmichael, and Chen Wei Tseng XAPP987 v1.0 March 18, 2008 Summary This application note discusses different aspects of single-event upsets and recommends	Original	XAPP987 XAPP987 voter XAPP988 XAPP216 RAM SEU fpga radiation CREME96 Upsets XAPP779 XQR2V6000	PDF
Synplify tmr Abstract: voter vhdl code for a grey-code counter CC16CE MUXCY CC16SE SRL16 XAPP197 XAPP216 vhdl coding for hamming code Text: Application Note: Virtex Series R XAPP197 v1.0.1 July 6, 2006 Triple Module Redundancy Design Techniques for Virtex FPGAs Author: Carl Carmichael Summary Triple Module Redundancy (TMR) combined with Single Event Upset (SEU) correction through partial reconfiguration is a powerful and effective SEU mitigation strategy. This method is only	Original	XAPP197 XAPP216, XAPP216 Synplify tmr voter vhdl code for a grey-code counter CC16CE MUXCY CC16SE SRL16 XAPP197 vhdl coding for hamming code	PDF
matched filter in vhdl Abstract: XAPP012 Insight Spartan-II demo board vhdl code for crossbar switch XAPP029 verilog code for cdma transmitter FPGA Virtex 6 pin configuration xapp005 verilog code for 16 kb ram verilog code for crossbar switch Text: DataSource CD-ROM Q4-01 Xilinx Application Notes Summaries Title Size Summary Family Design Loadable Binary Counters 40 KB XAPP004 XC3000 VIEWlogi OrCAD Register Based FIFO 60 KB XAPP005 XC3000 VIEWlogi OrCAD Boundary Scan Emulator for XC3000 80 KB XAPP007 XC3000	Original	Q4-01 XC3000 XC4000E XC4000 XC4000/XC5200 matched filter in vhdl XAPP012 Insight Spartan-II demo board vhdl code for crossbar switch XAPP029 verilog code for cdma transmitter FPGA Virtex 6 pin configuration xapp005 verilog code for 16 kb ram verilog code for crossbar switch	PDF
XAPP029 Abstract: adc controller vhdl code verilog rtl code of Crossbar Switch 12-bit ADC interface vhdl code for FPGA vhdl code for pn sequence generator Insight Spartan-II demo board XAPP172 xilinx XC3000 SEU testing verilog hdl code for triple modular redundancy parallel to serial conversion vhdl IEEE paper Text: DataSource CD-ROM Q4-01 Xilinx Application Note Summaries XAPP004 Loadable Binary Counters The design strategies for loadable and non-loadable binary counters are significantly different. This application note discusses the differences, and describes the design of a loadable binary counter.	Original	Q4-01 XAPP004 XAPP005 XC3000 Desi49 XC18V00, XC9500XL, XC9500XV, XAPP501 XC9500, XAPP029 adc controller vhdl code verilog rtl code of Crossbar Switch 12-bit ADC interface vhdl code for FPGA vhdl code for pn sequence generator Insight Spartan-II demo board XAPP172 xilinx XC3000 SEU testing verilog hdl code for triple modular redundancy parallel to serial conversion vhdl IEEE paper	PDF
32 BIT ALU design with vhdl Xilinx ISE 8.2i Abstract: xc4fx20-10ff672 ML405 ucf file 83-ISP UG156 32 BIT ALU design with vhdl RAMB16 XAPP1004 XC4VFX20 ML405 Text: Application Note: Virtex-4 FX FPGAs Single-Event Upset Mitigation Design Flow for Xilinx FPGA PowerPC Systems R XAPP1004 v1.0 March 14, 2008 Summary Authors: Greg Miller, Carl Carmichael, and Gary Swift Orbital, space-based, and extra-terrestrial applications are susceptible to the effects of high	Original	XAPP1004 32 BIT ALU design with vhdl Xilinx ISE 8.2i xc4fx20-10ff672 ML405 ucf file 83-ISP UG156 32 BIT ALU design with vhdl RAMB16 XAPP1004 XC4VFX20 ML405	PDF
UG156 Abstract: single port ram testbench vhdl SRL16 XAPP962 XAPP987 Virtex-4 radiation XAPP1004 XAPP216 XC2VP40 XC4VLX200 Text: Application Note: Virtex-II, and Virtex-4 FPGAs R XAPP962 v1.1 March 14, 2008 Summary Single-Event Upset Mitigation for Xilinx FPGA Block Memories Authors: Greg Miller, Carl Carmichael, and Gary Swift Orbital, space-based, and extra-terrestrial applications are susceptible to the effects of highenergy charged particles. If of sufficient energy, these particles can cause single-event upsets	Original	XAPP962 UG156 single port ram testbench vhdl SRL16 XAPP962 XAPP987 Virtex-4 radiation XAPP1004 XAPP216 XC2VP40 XC4VLX200	PDF
XAPP186 Abstract: XC4025E-4PG299 XC3090-100PG175 XC4013E-4CB228 XAPP151 XQ4036XL-3HQ240N XC3042-100PG84 XQ4028EX4HQ240N XC3042-100PG132 5962-9752501QYC Text: R 0 0 July 1, 2000 v1.0 The Website is Always Current Important Information You Need to Know About This Data Book Whenever Xilinx updates technical data on its products, the first place that information goes is to the Xilinx website. To find the absolutely latest technical product data from Xilinx, simply go	Original		PDF