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    38K15 Search Results

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    38K15 Price and Stock

    Vishay Intertechnologies PTF5638K150BXEK

    PTF-56 38.15K .1% T-10 EK e3 - Bulk (Alt: PTF5638K150BXEK)
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    Avnet Americas PTF5638K150BXEK Bulk 30 Weeks 100
    • 1 -
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    • 100 $9.5316
    • 1000 $2.65776
    • 10000 $2.65776
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    Vishay Intertechnologies PTF5638K150BXBF

    PTF-56 38.15K .1% T-10 B14 - Bulk (Alt: PTF5638K150BXBF)
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    Avnet Americas PTF5638K150BXBF Bulk 30 Weeks 100
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    • 100 $9.52113
    • 1000 $2.65882
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    Mouser Electronics PTF5638K150BXBF
    • 1 -
    • 10 $13.66
    • 100 $9.72
    • 1000 $8.75
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    TTI PTF5638K150BXBF Bulk 200 10
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    • 100 $0.95
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    Pizzato Elettrica Srl FM 538-K15

    Position switch for rotating levers | Pizzato USA FM 538-K15
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    RS FM 538-K15 Bulk 8 Weeks 1
    • 1 $36.21
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    • 100 $36.21
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    Pizzato Elettrica Srl FR 538-K15

    Position switch for rotating levers | Pizzato USA FR 538-K15
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    RS FR 538-K15 Bulk 8 Weeks 1
    • 1 $27.05
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    Pizzato Elettrica Srl FR 538-K15V9

    Position switch for rotating levers | Pizzato USA FR 538-K15V9
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    RS FR 538-K15V9 Bulk 8 Weeks 1
    • 1 $27.72
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    38K15 Datasheets Context Search

    Catalog Datasheet MFG & Type Document Tags PDF

    38K30

    Abstract: DELTA39K
    Text: USE DELTA39K FOR Quantum38K™ ISR™ ALL NEW DESIGNS CPLD Family CPLDs Designed for Migration Features • High density — 30K to 100K usable gates — 512 to 1536 macrocells — 136 to 302 maximum I/O pins — Eight dedicated inputs including four clock pins and


    Original     		DELTA39KTM Quantum38KTM 16-Kb 48-Kb 125-MHz 18-mm Quantum38K30 Quantum38K50 Quantum38K Delta39K 38K30 PDF

    100K preset horizontal

    Abstract: LB 124 d LB 124 transistor verilog code for implementation of eeprom 38K30 j510
    Text: Quantum38K ISR™ CPLD Family PRELIMINARY CPLDs Designed for Migration Features • High density — 30K to 100K usable gates — 512 to 1536 macrocells — 136 to 302 maximum I/O pins — Eight Dedicated Inputs including four clock pins and four global I/O control signal pins; four JTAG interface pins for reconfigurability/boundary scan


    Original     		Quantum38KTM CY38K100 208-pin 208EQFP) Quantum38K30 Quantum38K50 Quantum38K 100K preset horizontal LB 124 d LB 124 transistor verilog code for implementation of eeprom 38K30 j510 PDF

    Untitled

    Abstract: No abstract text available
    Text: Quantum38K ISR™ CPLD Family CPLDs Designed for Migration Features • High density — 30K to 100K usable gates — 512 to 1536 macrocells — 136 to 302 maximum I/O pins — Eight dedicated inputs including four clock pins and four global I/O control signal pins; four JTAG


    Original     		Quantum38Kâ 125-MHz 18-mm Quantum38K30 Quantum38K50 Quantum38K PDF

    Untitled

    Abstract: No abstract text available
    Text: Quantum38K ISR™ CPLD Family PRELIMINARY CPLDs at ASIC Prices™ Features • High density — 30K to 100K usable gates — 512 to 1536 macrocells — 136 to 302 maximum I/O pins — 8 Dedicated Inputs including 4 clock pins and 4 global I/O control signal pins; 4 JTAG interface pins


    Original     		Quantum38KTM 38K15 144FBGA MIL-STD-883" /JESD22-A114-A 83MHz 66MHz" 125MHz 83MHz" Quantum38K PDF

    208EQFP

    Abstract: No abstract text available
    Text: Quantum38K ISR™ CPLD Family CPLDs Designed for Migration Features • High density — 30K to 100K usable gates — 512 to 1536 macrocells — 136 to 302 maximum I/O pins — Eight dedicated inputs including four clock pins and four global I/O control signal pins; four JTAG


    Original     		Quantum38KTM 125-MHz 18-mm Quantum38K30 Quantum38K50 Quantum38K 208EQFP PDF

    CY3LV010

    Abstract: 38K30 CYDH2200E 38K50
    Text: Quantum38K ISR™ CPLD Family PRELIMINARY CPLDs at ASIC Prices™ Features • High density — 30K to 100K usable gates — 512 to 1536 macrocells — 136 to 302 maximum I/O pins — Eight Dedicated Inputs including four clock pins and four global I/O control signal pins; four JTAG interface pins for reconfigurability/boundary scan


    Original     		Quantum38KTM Quantum38K CY38K100 208-pin 208EQFP) CY3LV010 38K30 CYDH2200E 38K50 PDF

    WIDE BUS FAMILY

    Abstract: No abstract text available
    Text: Quantum38K ISR™ CPLD Family PRELIMINARY CPLDs at ASIC Prices™ Features • High density — 15K to 100K usable gates — 256 to 1536 macrocells — 92 to 302 maximum I/O pins — 8 Dedicated Inputs including 4 clock pins and 4 global control signal pins; 4 JTAG interface pins for


    Original     		Quantum38KTM WIDE BUS FAMILY PDF

    38K30

    Abstract: DELTA39K CY3LV010
    Text: USE DELTA39K FOR Quantum38K™ ISR™ ALL NEW DESIGNS CPLD Family CPLDs Designed for Migration Features • High density — 30K to 100K usable gates — 512 to 1536 macrocells — 136 to 302 maximum I/O pins — Eight dedicated inputs including four clock pins and


    Original     		DELTA39KTM Quantum38KTM 16-Kb 48-Kb 125-MHz 18-mm Quantum38K30 Quantum38K50 Quantum38K Delta39K 38K30 CY3LV010 PDF