K7Z327285M

Contextual Info: K7Z327285M Preliminary 512Kx72 DLW Double Late Write RAM Document Title 512Kx72 DLW(Double Late Write) RAM Revision History Rev. No. 0.0 0.1 History Draft Date Remark 1. Initial document. 1. Device name change from Double Late Write SigmaRAM to Double Late Write RAM

K7N327245M

Abstract: K7N327249M
Contextual Info: Preliminary 512Kx72 Pipelined NtRAMTM K7N327245M Document Title 512Kx72-Bit Pipelined NtRAM TM Revision History Rev. No. 0.0 0.1 History Draft Date Remark 1. Initial document. 1. Speed bin merge. From K7N327249M to K7N327245M 2. AC parameter change. tOH min /tLZC(min) from 0.8 to 1.5 at -25

BB209

Abstract: CYM52KNP72V33A-10BBC CYM52KNP72V33A-13BBC CYM52KNP72V33A-15BBC
Contextual Info: PRELIMINARY CYM52KNP72AV33 512Kx72 Pipelined MCM with NoBL Architecture Features • No Bus Latency, no dead cycles between write and read cycles • Internally synchronized registered outputs eliminate the need to control OE • Single 3.3V –5% and +5% power supply VDD

Contextual Info: Preliminary 512Kx72 Pipelined NtRAM TM K7N327245M Document Title 512Kx72-Bit Pipelined NtRAMTM Revision History History Draft Date Remark 0.0 0.1 1. Initial document. 1. Speed bin merge. From K7N327249M to K7N327245M 2. AC parameter change. tOH min /tLZC(min) from 0.8 to 1.5 at -25

C50456

Contextual Info: WEDPZ512K72V-XBX HI-RELIABILITY PRODUCT 512Kx72 Synchronous Pipeline Burst ZBL SRAM ADVANCED* FEATURES DESCRIPTION • Fast clock speeds: 166, 133, 100MHz The WEDPZ512K72V-XBX employs high-speed, low-power CMOS designs that are fabricated using an advanced CMOS process. The

K7N327245M

Contextual Info: Preliminary 512Kx72 Pipelined NtRAMTM K7N327245M 512Kx72-Bit Pipelined NtRAM TM FEATURES GENERAL DESCRIPTION • 2.5V ±5% Power Supply. • Byte Writable Function. • Enable clock and suspend operation. • Single READ/WRITE control pin. • Self-Timed Write Cycle.

K7N327249M

Contextual Info: Preliminary 512Kx72 Pipelined NtRAMTM K7N327249M 512Kx72-Bit Pipelined NtRAM TM FEATURES GENERAL DESCRIPTION • 2.5V ±5% Power Supply. • Byte Writable Function. • Enable clock and suspend operation. • Single READ/WRITE control pin. • Self-Timed Write Cycle.

Contextual Info: WPY512K72V-XMDC M/HITE /MICROELECTRONICS 4MByte 512Kx72 Flow Through Synchronous SRAM Module ADVAN CED * FEATURES • Fast A c c e s s Tim es: 8, 10ns ■ Byte W rite and Global W rite C ap ab ilitie s ■ Fast OE A c c e s s Tim e of 4ns ■ Flo w th ro u gh Data Bus (2-1-1-1 burst)

Contextual Info: WPY512K72V-XMDC M/HITE /MICROELECTRONICS 4MByte 512Kx72 Flow Through Synchronous SRAM Module A DVA N CED * FEATURES • Fast A cce ss Tim es: 8 , 1 0ns ■ Byte W r i t e and Global W r i t e C ap a b ilities ■ Fast OE A cce ss Tim e o f 4ns ■ F lo w t h r o u g h Data Bus (2-1-1 -1 burst)

C50456

Contextual Info: WEDPZ512K72V-XBX HI-RELIABILITY PRODUCT 512Kx72 ZBT Synchronous Pipeline SRAM ADVANCED* FEATURES DESCRIPTION • Fast clock speeds: 166, 133, 100MHz The WEDPZ512K72V-XBX employs high-speed, low-power CMOS designs that are fabricated using an advanced CMOS process. The

Contextual Info: a WHITE /MICROELECTRONICS W PY512K72V-XMDC 4MByte 512Kx72 Flow Through Synchronous SRAM Module A D VAN CED * FEATURES • Fast A c c e s s T im e s : 8, 10ns ■ Byte W r i t e a n d G lo b a l W r i t e C a p a b i lit i e s ■ Fast OE A c c e s s T i m e o f 4 ns

NtRAM

Abstract: K7N327245M K7N327249M
Contextual Info: Preliminary 512Kx72 Pipelined NtRAM TM K7N327245M Document Title 512Kx72-Bit Pipelined NtRAMTM Revision History History Draft Date Remark 0.0 1. Initial document. May. 10. 2001 Advance 0.1 1. Speed bin merge. From K7N327249M to K7N327245M 2. AC parameter change.

W2Z512K72SJ

Contextual Info: W2Z512K72SJ 36Mb, 512Kx72 Synchronous Pipeline Burst NBL SRAM Preliminary* FEATURES DESCRIPTION n Fast clock speed: 225, 200, 166 and 150MHz The WEDC SyncBurst - SRAM family employs highspeed, low-power CMOS designs that are fabricated using an advanced CMOS process. WEDC’s 72Mb

9261A

Abstract: CYM9260 CYM9263 PM44 9261
Contextual Info: fax id: 2042 3g~ yr pyprfs^ PRELIMINARY CYM9260 CYM9261A/B CYM9262A/B CYM9263 64K x 72 SRAM 128K x 72 SRAM 256K x 72 SRAM 512K x 72 SRAM Features Module Module Module Module 9262B, 9263 SRAM’s in plastic surface mount packages on an epoxy laminate board with pins. The modules are designed

Contextual Info: K7N323601M K7N321801M 1Mx36 & 2Mx18 Pipelined NtRAMTM Document Title 1Mx36 & 2Mx18-Bit Pipelined NtRAMTM Revision History Rev. No. 0.0 0.1 0.2 0.3 0.4 0.5 1.0 History Draft Date Remark 1. Initial document. 1. Add 165FBGA package 1. Update JTAG scan order 2. Speed bin merge.

CY7C1461V25

Abstract: CY7C1463V25 CY7C1465V25
Contextual Info: CY7C1461V25 CY7C1463V25 CY7C1465V25 PRELIMINARY 1M x 36/2M x 18/512K x 72 Flow-Thru SRAM with NoBL Architecture Features • Zero Bus Latency, no dead cycles between Write and Read cycles •Supports 133-MHz bus operations •1M x 36/2M × 18/512K × 72 common I/O

BE5L

Abstract: CYD18S18V18 CYD09S36V18 CYD18S36V18 SKR 175 FullFlex36
Contextual Info: FullFlex FullFlex Synchronous SDR Dual Port SRAM Features Functional Description • True dual port memory enables simultaneous access to the shared array from each port ■ Synchronous pipelined operation with Single Data Rate SDR operation on each port

FullFlex36

Contextual Info: FullFlex FullFlex Synchronous DDR Dual-Port SRAM Features • True dual-ported memory allows simultaneous access to the shared array from each port • Synchronous pipelined operation with selectable Double Data Rate DDR or Single Data Rate (SDR) operation on each port

FullFlex36

Contextual Info: PRELIMINARY FullFlex Synchronous DDR Dual-Port SRAM Features • True dual-ported memory allows simultaneous access to the shared array from each port • Synchronous pipelined operation with selectable Double Data Rate DDR or Single Data Rate (SDR) operation on each port

FullFlex36

Contextual Info: FullFlex FullFlex Synchronous DDR Dual-Port SRAM Features • True dual-ported memory allows simultaneous access to the shared array from each port • Synchronous pipelined operation with selectable Double Data Rate DDR or Single Data Rate (SDR) operation on each port

CY7C1440V33

Contextual Info: CY7C1440V33 CY7C1442V33 CY7C1446V33 PRELIMINARY 1M x 36/2M x 18/512K x 72 Pipelined SRAM Features • • • • • • • • • • • • • • • • Fast clock speed: 250, 200, and 167 MHz Provide high-performance 3-1-1-1 access rate Fast access time: 2.7, 3.0 and 3.5 ns

K7N321845M

Abstract: K7N323645M
Contextual Info: K7N323645M K7N321845M Preliminary 1Mx36 & 2Mx18 Pipelined NtRAMTM Document Title 1Mx36 & 2Mx18-Bit Pipelined NtRAMTM Revision History Rev. No. 0.0 0.1 0.2 0.3 0.4 History Draft Date Remark 1. Initial document. 1. Add 165FBGA package 1.Update JTAG scan order

K7M321825M

Abstract: K7M323625M
Contextual Info: K7M323625M K7M321825M Preliminary 1Mx36 & 2Mx18 Flow-Through NtRAMTM Document Title 1Mx36 & 2Mx18-Bit Flow Through NtRAMTM Revision History Rev. No. 0.0 0.1 0.2 0.3 0.4 0.5 History Draft Date Remark 1. Initial document. 1. Add 165FBGA package 1. Update JTAG scan order

250ac to 30 v ac

Abstract: CY7C1462V25 CY7C1464V25 CY7C1460V25
Contextual Info: CY7C1460V25 CY7C1462V25 CY7C1464V25 PRELIMINARY 1M x 36/2M x 18/512K x 72 Pipelined SRAM with NoBL Architecture Features • Zero Bus Latency, no dead cycles between write and read cycles • Fast clock speed: 250, 200, and 167 MHz • Fast access time: 2.7, 3.0 and 3.5 ns