DOCUMENTATION OF SHADOW ALARM
Abstract: ndf 020-21
Text: T1Mx28 Device DS1 Mapper 28-Channel TXC-04228 TECHNICAL OVERVIEW PRODUCT PREVIEW FEATURES DESCRIPTION • Twenty-eight independent 1.544 Mbit/s DS1 mappers • Single/dual byte-parallel Telecom Bus @ 6.48 MHz 28 slots or 19.44 MHz (84 slots) • Floating VT1.5 byte-synchronous mapping for use
|
Original
|
T1Mx28
28-Channel
TXC-04228
VC-4/AU-3/TU-11)
5/TU-11
DOCUMENTATION OF SHADOW ALARM
ndf 020-21
|
PDF
|
80960SA
Abstract: 80960SB 65A176 AD427
Text: 80960SA EMBEDDED 32-BIT MICROPROCESSOR WITH 16-BIT BURST DATA BUS • High-Performance Embedded ■ Pin Compatible with 80960SB Architecture — 20 MIPS* Burst Execution at 20 MHz — 7.5 MIPS Sustained Execution at 20 MHz ■ 512-Byte On-Chip Instruction Cache
|
Original
|
80960SA
32-BIT
16-BIT
80960SB
512-Byte
80960SA
80960SB
65A176
AD427
|
PDF
|
bms 16s
Abstract: SWBT13 UT1553BCRTM ta306
Text: UT1553 BCRTM p Register-oriented architecture to enhance FEATURES p Comprehensive MIL-STD-1553 dual-redundant Bus p p p p p programmability p DMA memory interface with 64K addressability p Internal self-test p Radiation-hardened option available for 84-lead
|
Original
|
UT1553
MIL-STD-1553
MIL-STD-1773
84-lead
84-pin
84lead
MIL-M-38510.
36-Lead
Packaging-10
bms 16s
SWBT13
UT1553BCRTM
ta306
|
PDF
|
SWBT13
Abstract: rta2 1553b rti
Text: UT1553B BCRT p Register-oriented architecture to enhance FEATURES p Comprehensive MIL-STD-1553B dual-redundant programmability p DMA memory interface with 64K addressability p Internal self-test p Remote terminal operations in ASD/ENASD-certified Bus Controller BC and Remote Terminal
|
Original
|
UT1553B
MIL-STD-1553B
MIL-STD-1773
84-pin
132-lead
84-lead
MIL-M-38510.
36-Lead
Packaging-10
SWBT13
rta2
1553b rti
|
PDF
|
fp6160
Abstract: rta2
Text: UT1553B BCRT p Register-oriented architecture to enhance FEATURES p Comprehensive MIL-STD-1553B dual-redundant programmability p DMA memory interface with 64K addressability p Internal self-test p Remote terminal operations in ASD/ENASD-certified Bus Controller BC and Remote Terminal
|
Original
|
UT1553B
MIL-STD-1553B
MIL-STD-1773
84-pin
132-lead
84-lead
MIL-M-38510.
36-Lead
Packaging-10
fp6160
rta2
|
PDF
|
common mode rejection ratio test 1553B
Abstract: rta2 1553 SUmmit
Text: 1.0 INTRODUCTION The monolithic SµMMIT provides the system designer with an intelligent solution to MIL-STD-1553 multiplexed serial data bus design problems. The SµMMIT is a single-chip device that implements all three of the defined MIL-STD-1553 functions Remote Terminal, Bus Controller, and Monitor. Operating either
|
Original
|
MIL-STD-1553
139-pin
140-pin
V/15V
V/12V
common mode rejection ratio test 1553B
rta2
1553 SUmmit
|
PDF
|
DS51140
Abstract: DS51298 PIC32 PICC-18 44-pin plcc pcb mount footprint 44L PLCC socket XLT18SO-1
Text: Transition Socket Specification 2010 Microchip Technology Inc. DS51194S Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. •
|
Original
|
DS51194S
DS51194S-page
DS51140
DS51298
PIC32
PICC-18
44-pin plcc pcb mount footprint
44L PLCC socket
XLT18SO-1
|
PDF
|
Untitled
Abstract: No abstract text available
Text: STP2021 S un M ic r o e l e c t r o n ic s J u ly 1997 PMC Power Management Controller DATA SHEET D e s c r ip t io n The STP2021 Power Management Controller brings power management to SBus-based systems. The STP2021 interfaces to the SBus via the byte-wide expansion bus EBus provided by the STP2001 Slave I/O Controller.
|
OCR Scan
|
STP2021
STP2021
STP2001
84-Lead
TP2021PLC
84-Pin
|
PDF
|
vp44
Abstract: CY37064 CY37064V
Text: «oaHaoooiMMMWfMMMMMM!9:^ v’*'» -^ jjÉBT * ¿f5 ’00“’'* '^ 7“T{• < 1; .r - - •■■■■■■ c PRELIMINARY CY37064V 3, £ ,.* k v / k J UltraLogic 3.3V 64-Macrocell ISR™CLPD — tPD = 8.5ns Features — ts = 5.0 ns • 64 macrocells in four logic blocks
|
OCR Scan
|
CY37064V
64-Macrocell
vp44
CY37064
CY37064V
|
PDF
|
cy37128
Abstract: CY37128P160-125AC CY37128V CY7C375 CY37128P84-125JI cy3700
Text: = m m m !Æ '^ r ^ r : c Q CY3 7 1 2 8 PR £um A ^Y UltraLogic 128-Macrocell ISR™ CPLD — tco = 4.0 ns Features • • • • • • • • • • • 128 macrocells in eight logic blocks • In-System Reprogrammable™ ISR™ — JTAG-compliant on-board programming
|
OCR Scan
|
CY37128
128-Macrocell
cy37128
CY37128P160-125AC
CY37128V
CY7C375
CY37128P84-125JI
cy3700
|
PDF
|
CY101E383
Abstract: E383 99s1
Text: fax id: 5000 ,.V.Ï.Ï.V.^ y nr' Æ C Y 101E383 CYPRESS ECL/TTL/ECL Translator and High-Speed Bus Driver Features • BiCMOS for optimum speed/power • High speed max. — 2.5 ns tpQ TTL-to-ECL — 3 ns tpQ ECL-to-TTL Low skew < ± 1 ns Can operate on single +5V supply
|
OCR Scan
|
80-pin
CY101E383
CY101E383
E383
99s1
|
PDF
|
UNITED TECHNOLOGIES MICROELECTRONICS CENTER
Abstract: No abstract text available
Text: Military Standard Products UT 1553 RTMP Remote Terminal Multi-Protocol Product Brief UNITED TECHNOLOGIES MICROELECTRONICS CENTER April 1988 FEATURES □ □ All h a n d sh a k in g signals p ro v id e d for D M A m em ory access im p lem en tatio n C om plete M IL -S T D -1 5 5 3 re m o te term in al
|
OCR Scan
|
UT1553RTMP
84-pin
84-lead
RTMP-2-4-88-PB
UNITED TECHNOLOGIES MICROELECTRONICS CENTER
|
PDF
|
84 PIN CERAMIC QUAD FLAT PACK
Abstract: 2600 corning cypress flash 370 7C374-100 7C374-66 7C374L-66 CY7C373 CY7C374 FLASH370 CY7C374-83GC
Text: fax id: 6129 —— — - = : ! W Æ j r I 1 CY7C374 17 Q Q IT C O O UltraLogic 128-Macrocell Flash CPLD Features The logic blocks in the FLASH370 architecture are connected with an extremely fast and predictable routing resource— the Programmable Interconnect Matrix PIM . The PIM brings flex
|
OCR Scan
|
CY7C374
128-Macrocell
84-pin
100-pin
CY7C373
CY7C374
ASH370t
FLASH370
84 PIN CERAMIC QUAD FLAT PACK
2600 corning
cypress flash 370
7C374-100
7C374-66
7C374L-66
CY7C374-83GC
|
PDF
|
RS-343-A
Abstract: RS-343A BT458
Text: ADVANCED MICRO DEVICES *ÌL> D È | DSS7S5S 00203^5 1 Am81C81/Am81C82 • 28365 D T-SZ -33 - 09 CMOS Color Palette a ADVANCE INFORMATION > 3 co DISTINCTIVE CHARACTERISTICS Am81C81 On-chip phase-k>d<ed loop eliminates the need for ECL on PC board On-chip video timing generator
|
OCR Scan
|
Am81C81/Am81C82
Am81C81
84-pin
RS-343A
Am81C82
Bt458
ceramic-PGrr61C81orfy.
CP-7M-1/88-0
RS-343-A
|
PDF
|
|
|
est 7502 b data sheet
Abstract: No abstract text available
Text: P E H I1 0 IM 1 D B M IV i n Dt t e : s. i 991 82495XP CACHE CONTROLLER/ 82490XP CACHE RAM • Two-Way, Set Associative, Secondary Cache for i860 XP Microprocessor MESI Cache Consistency Protocol ■ 50 MHz “No Glue” Interface with CPU Maintains Consistency with Primary
|
OCR Scan
|
82495XP
82490XP
10-3a.
Controller/82490XP
est 7502 b data sheet
|
PDF
|
Untitled
Abstract: No abstract text available
Text: 87C196CA/87C196CB 20 MHz ADVANCED 16-BIT CHMOS MICROCONTROLLER WITH INTEGRATED CAN 2.0 Automotive m High Performance CHMOS 16-Bit CPU • Full Duplex Synchronous Serial I/O Port SSIO (up to 20 MHz Operation) ■ Register-Register Architecture ■ Up to 56 Kbytes of On-Chip EPROM
|
OCR Scan
|
87C196CA/87C196CB
16-BIT
87C196CB.
87C196CA,
87C196CB,
|
PDF
|
Untitled
Abstract: No abstract text available
Text: in tj 80960SB EMBEDDED 32-BIT MICROPROCESSOR WITH 16-BIT BURST DATA BUS • High-Performance Embedded Architecture — 16 MIPS* Burst Execution at 16 MHz — 5 MIPS Sustained Execution at 16 MHz ■ Built-In Interrupt Controller — 4 Direct Interrupt Pins
|
OCR Scan
|
80960SB
32-BIT
16-BIT
512-Byte
16-Bit
8096SA
4fl2bl75
|
PDF
|
Untitled
Abstract: No abstract text available
Text: in te l 8XC196MC INDUSTRIAL MOTOR CONTROL MICROCONTROLLER 87C196MC 16 Kbytes of On-Chip OTPROM* 83C196MC 16 Kbytes of On-Chip ROM High Performance CHMOS 16-Bit CPU 16 Kbytes of On-Chip OTPROM/ROM 488 bytes of On-Chip Register RAM Register to Register Architecture
|
OCR Scan
|
8XC196MC
87C196MC
83C196MC
16-Bit
8/10-Bit
|
PDF
|
84-PIN
Abstract: CY7C341B
Text: CY7C341B y CYPRESS Features • 192 macrocells in 12 LABs • 8 dedicated inputs, 64 bidirectional I/O pin • Advanced 0.65-micron CMOS technology to increase performance • Programmable interconnect array • 384 expander product terms • Available in 84-pin HLCC, PLCC, and
|
OCR Scan
|
CY7C341B
65-micron
84-pin
CY7C341B
CY7C341Bis
35RC/RI
84-Lead
CY7C341Bâ
35HMB
|
PDF
|
Ultra37064
Abstract: CERAMIC LEADLESS CHIP CARRIER CY7C372 CY7C373 ieee1149.1 cypress
Text: J ^ m n rn n : if : Y PRELIMINARY H Ultra37064 - UltraLogic 64-Macrocell ISR™ CPLD Features — ts = 3.5 ns — tc o = 4.5 ns • 64 m a cro cells in fo u r logic blocks • P ro d uct-term clocking • In-S ystem R ep ro g ra m m ab le ™ IS R ™
|
OCR Scan
|
Ultra37064
64-Macrocell
167MHz
IEEE1149
Ultra37064
CERAMIC LEADLESS CHIP CARRIER
CY7C372
CY7C373
ieee1149.1 cypress
|
PDF
|
MX 0541
Abstract: mx 0541 b CY7C373
Text: fax id: 6138 CY7C373Ì CYPRESS UltraLogic 64-Macrocell Flash CPLD Functional Description Features • 64 m a cro cells in fo u r logic blocks The C Y 7 C 3 73i is an In-System R eprogram m able C om plex P rogram m able Logic Device CPLD and is pa rt of the
|
OCR Scan
|
CY7C373Ã
64-Macrocell
84-pin
100-pin
CY7C374i
CY7C373i
FLASH370iâ
MX 0541
mx 0541 b
CY7C373
|
PDF
|
K12J
Abstract: 100-PIN CY7C346 CY7C346B f 7400
Text: CY7C346 CY7C346B 5T CYPRESS 128-Macrocell MAX EPLDs Features Functional Description • 128 macrocells in 8 LABs • 20 dedicated inputs, up to 64 bidirec tional I/O pins • Programmable interconnect array • 0.8-micron double-metal CMOS EPROM technology CY7C346
|
OCR Scan
|
CY7C346
CY7C346B
CY7C346)
65-micron
CY7C346B)
84-pin
100-pin
128-Macrocell
CY7C346/CY7C346B
CY7C346/
K12J
CY7C346B
f 7400
|
PDF
|
NSf39
Abstract: IR 0251 CY7C024 CY7C0241 CY7C025 CY7C0251 017L
Text: fax id: 5206 CY7C024/0241 CY7C025/0251 4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with Sem, Int, Busy Features Functional Description • True D u al-P o rted m em o ry ce lls w h ich allow s im u ltan eo u s reads of th e s a m e m e m o ry location • 4K x 16 o rg an iza tio n C Y 7 C 02 4
|
OCR Scan
|
CY7C024/0241
CY7C025/0251
CY7C024)
CY7C0241)
CY7C025)
CY7C0251)
65-micron
84-Lead
CY7C024/0241
NSf39
IR 0251
CY7C024
CY7C0241
CY7C025
CY7C0251
017L
|
PDF
|
CY101E383
Abstract: E383 E1472
Text: fax id: 5000 i , *" : :V:V:V:V:V:g:-v- : : ^ :^ ; ^3»* i ; : M m : M : i : m : CY101E383 ECL/TTL/ECL Translator and High-Speed Bus Driver Features • BiCMOS for optimum speed/power • High speed max. — 3.0 ns tpQ TTL-to-ECL — 4 ns tpQ ECL-to-TTL
|
OCR Scan
|
80-pin
84-pin
CY101E383
CY101E383
E383
E1472
|
PDF
|