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    Lattice Semiconductor Corporation LCMXO3L-1300C-5BG256C

    IC FPGA 206 I/O 256CABGA
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    DigiKey LCMXO3L-1300C-5BG256C Tray 2,961 1
    • 1 $12.65
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    Lattice Semiconductor Corporation LCMXO2-4000HE-4BG256I

    IC FPGA 206 I/O 256CABGA
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    DigiKey LCMXO2-4000HE-4BG256I Tray 1,566 1
    • 1 $25.85
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    Lattice Semiconductor Corporation LCMXO2-7000HC-4BG256C

    IC FPGA 206 I/O 256CABGA
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    DigiKey LCMXO2-7000HC-4BG256C Tray 741 1
    • 1 $27.7
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    Lattice Semiconductor Corporation LCMXO3D-9400HC-5BG256I

    IC FPGA 206 I/O 256CABGA
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    DigiKey LCMXO3D-9400HC-5BG256I Tray 654 1
    • 1 $35.45
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    Lattice Semiconductor Corporation LCMXO2-4000HC-6BG256I

    IC FPGA 206 I/O 256CABGA
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    DigiKey LCMXO2-4000HC-6BG256I Tray 627 1
    • 1 $29.75
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    BG256 Datasheets (1)

    Part ECAD Model Manufacturer Description Curated Datasheet Type PDF
    BG256 Cypress Semiconductor Ball Grid Array Packages Original PDF

    BG256 Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    Untitled

    Abstract: No abstract text available
    Text: Product Obsolete/Under Obsolescence R XC4000XLA Family Field Programmable Gate Arrays Package Pinouts XC4013XLA Pinout Table XC4013XLA Pinout Table Continued XC4013XLA Pinout Table PAD NAME PQ160 PQ208 PQ240 I/O – – P21 BG256 H1 PAD NAME PQ160 PQ208


    Original     		PDF XC4000XLA XC4013XLA PQ160 PQ208 PQ240 BG256

    BG256

    Abstract: No abstract text available
    Text: R Plastic BGA BG256 Package PK018 (v1.0) June 1, 2000 2000 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm. All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.


    Original     		PDF BG256) PK018 BG256

    BG256

    Abstract: BG352 352-LEAD
    Text: Package Diagrams Ball Grid Array Packages 119-Lead FBGA 14 x 22 x 2.4 mm BG119 51-85115 1 Package Diagrams 256-Lead Ball Grid Array (27 x 27 x 2.33 mm) BG256 51-85097 2 Package Diagrams 352-Lead Ball Grid Array (35 x 35 x 2.33 mm) BG352 51-85103 3


    Original     		PDF 119-Lead BG119 256-Lead BG256 352-Lead BG352 BG256 BG352

    Diagrams

    Abstract: 5185143 BG-272 mold cap BG256 BG352 BG-209 Package Diagrams 14X22
    Text: Package Diagrams Ball Grid Array Packages 119-Lead PBGA 14 x 22 x 2.4 mm BG119 51-85115-*A 1 Package Diagrams 209-Lead PBGA (14 x 22 x 2.20 mm) BG209 51-85143-*A 2 Package Diagrams 256-Lead PBGA (27 x 27 x 2.33 mm) BG256 51-85097-*A 3 Package Diagrams 272-Lead Ball Grid Array (27 x 27 x 2.33 mm) BG272


    Original     		PDF 119-Lead BG119 209-Lead BG209 256-Lead BG256 272-Lead BG272 388-Lead BG352 Diagrams 5185143 BG-272 mold cap BG256 BG352 BG-209 Package Diagrams 14X22

    BGG256

    Abstract: PK018 BG256
    Text: R Plastic BGA BG256/BGG256 Package PK018 (v1.3) March 19, 2007 256-BALL PLASTIC BGA (BG256/BGG256) 2001, 2006, 2007 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.


    Original     		PDF BG256/BGG256) PK018 256-BALL BGG256 PK018 BG256

    Untitled

    Abstract: No abstract text available
    Text: R Plastic BGA BG256 Package PK018 (v1.1) April 6, 2001 2001 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm. All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.


    Original     		PDF BG256) PK018

    BG256

    Abstract: No abstract text available
    Text: BGA Packages - BG256 July 2, 1998 Version 1.3 10-33


    Original     		PDF BG256 BG256

    BG256

    Abstract: No abstract text available
    Text: BGA Packages - BG256 November 13, 1997 Version 1.2 10-33


    Original     		PDF BG256 BG256

    BG-272

    Abstract: 5185130
    Text: Package Diagrams Ball Grid Array Packages 119-Lead FBGA 14 x 22 x 2.4 mm BG119 51-85115 1 Package Diagrams 256-Lead Ball Grid Array (27 x 27 x 2.33 mm) BG256 51-85097 2 Package Diagrams 272-Lead Ball Grid Array (27 x 27 x 2.33 mm) BG272 51-85130 3 Package Diagrams


    Original     		PDF 119-Lead BG119 256-Lead BG256 272-Lead BG272 352-Lead BG352 BG-272 5185130

    BG256

    Abstract: No abstract text available
    Text: Package Diagram Ball Grid Array Packages 256-Lead Ball Grid Array 27 x 27 x 2.33 mm BG256 51-85097 1


    Original     		PDF 256-Lead BG256 BG256

    transistor bl p89

    Abstract: bl p74 transistor J955 XC4000 XC4000A XC4000D XC4000E XC4000EX XC4000H p180 g8
    Text: book XC4000E and XC4000X Series Field Programmable Gate Arrays R January 29, 1999 Version 1.5 6* XC4000E and XC4000X Series Features Note: XC4000 Series devices described in this data sheet include the XC4000E family and XC4000X Series. XC4000X Series devices described in this data sheet


    Original     		PDF XC4000E XC4000X XC4000 XC4000EX XC4000XL transistor bl p89 bl p74 transistor J955 XC4000A XC4000D XC4000H p180 g8

    CY37384

    Abstract: CY37384V
    Text: PRELIMINARY CY37384 UltraLogic 384-Macrocell ISR™ CPLD — tS = 5.5 ns Features • 384 macrocells in 24 logic blocks • In-System Reprogrammable™ ISR™ — JTAG-compliant on-board programming • • • • • • • • • • — Design changes don’t cause pinout changes


    Original     		PDF CY37384 384-Macrocell CY37384 CY37384V

    Untitled

    Abstract: No abstract text available
    Text: — OBSOLETE — OBSOLETE — OBSOLETE — OBSOLETE — OBSOLETE — QPRO XQ4000XL Series QML High-Reliability FPGAs R DS029 v2.0 March 7, 2014 2 XQ4000X Series Features • • • • • • • Certified to MIL-PRF-38535 Appendix A QML (Qualified Manufacturer Listing)


    Original     		PDF XQ4000XL DS029 XQ4000X MIL-PRF-38535 XQ4013XL XQ4036XL XQ4062XL XQ4085XL XQ4085XL-1 XCN07003,

    FPGA Virtex 6 pin configuration

    Abstract: Virtex CS144 TQ144 XCV100 XCV150 XCV200 XCV300 XCV50 xapp151
    Text: Virtex 2.5 V Field Programmable Gate Arrays R 3 Architectural Description The output buffer and all of the IOB control signals have independent polarity controls. VersaRing The Virtex architecture also includes the following circuits that connect to the GRM.


    Original     		PDF DS003-1, DS003-2, DS003-3, DS003-4, DS003-2 FPGA Virtex 6 pin configuration Virtex CS144 TQ144 XCV100 XCV150 XCV200 XCV300 XCV50 xapp151

    LCMXO2-1200HC-4TG100C

    Abstract: LCMXO2-256HC-4TG100I LCMXO2-1200 tn1200 lcmxo2 LCMXO2-1200HC-4TG100 LCMXO2-2000 LCMXO2-7000 MachXO2-1200 LCMXO2-4000HC
    Text: MachXO2 Family Handbook HB1010 Version 01.0, November 2010 MachXO2 Family Handbook Table of Contents November 2010 Section I. MachXO2 Family Data Sheet Introduction Features . 1-1


    Original     		PDF HB1010 LCMXO2-1200HC-4TG100C LCMXO2-256HC-4TG100I LCMXO2-1200 tn1200 lcmxo2 LCMXO2-1200HC-4TG100 LCMXO2-2000 LCMXO2-7000 MachXO2-1200 LCMXO2-4000HC

    qfn 3x3 tray dimension

    Abstract: XCDAISY BFG95 XC5VLX330T-1FF1738I pcb footprint FS48, and FSG48 WS609 jedec so8 Wire bond gap XC3S400AN-4FG400I FFG676 XC4VLX25 cmos 668 fcbga
    Text: Device Package User Guide [Guide Subtitle] [optional] UG112 v3.5 November 6, 2009 [optional] R R Xilinx is disclosing this user guide, manual, release note, and/or specification (the "Documentation") to you solely for use in the development of designs to operate with Xilinx hardware devices. You may not reproduce, distribute, republish, download, display, post, or transmit the


    Original     		PDF UG112 UG072, UG075, XAPP427, qfn 3x3 tray dimension XCDAISY BFG95 XC5VLX330T-1FF1738I pcb footprint FS48, and FSG48 WS609 jedec so8 Wire bond gap XC3S400AN-4FG400I FFG676 XC4VLX25 cmos 668 fcbga

    n20s

    Abstract: A144 BG256 IEEE1164 Military Plastic pASIC 3 Family 256
    Text: 3T PRELIMINARY CYPRESS Ultra38007 UltraLogic Very High Speed 7K Gate CMOS FPGA Features — Minimum Iol and Ioh 24 mA Flexible logic cell architecture — Wide fan-in up to 16 input gates — Multiple outputs in each cell — Very low cell propagation delay


    OCR Scan     		PDF 144-pin 208-pin 256-pin 16-bit Ultra38007 208-Pin CY38007P20 CY38007P144â n20s A144 BG256 IEEE1164 Military Plastic pASIC 3 Family 256

    CY37384

    Abstract: CY37384V L0651
    Text: = j— PRELIMINARY T. # CY37384V UltraLogic 3.3V 384-Macrocell ISR™ CPLD Fully Routable with 100% Logic Utilization Features — JTAG-compliant on-board programming The CY37384V is designed with a robust routing architecture which allows utilization of the entire device with a fixed pinout.


    OCR Scan     		PDF CY37384V 384-Macrocell CY37384 CY37384V L0651

    AAAG 6 pin ic

    Abstract: n208
    Text: CYPRESS Features PRELIMINARY UltraLogic Very High Speed 7K Gate CMOS FPGA — Minimum Iol and Ioh ° f 24 mA • Flexible logic cell architecture — Wide fan-in up to 16 input gates — Multiple outputs in each cell — Very low cell propagation delay


    OCR Scan     		PDF 144-Pin 256-Pad 208-Pin AAAG 6 pin ic n208

    Untitled

    Abstract: No abstract text available
    Text: QPRO XQ4000XL Serles QML flX IU N X High-Reliablllty Field Programmable Gate Arrays May 19, 1998 Version 1.0 XG4QQQX Series Features • • • • • • • • • • • • • • Certified to MIL-PRF-38535 Appendix A QML (Qualified Manufacturer Listing)


    OCR Scan     		PDF XQ4000XL MIL-PRF-38535 XQ4013XL XQ4036XL XQ4062XL A12IO A13IO A14IO 4062XL-3 MIL-PRF-38535â

    Untitled

    Abstract: No abstract text available
    Text: • ■ J ^ m n r n n PRELIMINARY Ultra37256 UltraLogic 256-Macrocell ISR™ CPLD — tco = 4.5 ns Features • 256 macrocells in sixteen logic blocks • In-System Reprogram mable ISR™ — JTAG-compliant on-board programming — Design changes don’t cause pinout changes


    OCR Scan     		PDF Ultra37256 256-Macrocell IEEE1149

    Untitled

    Abstract: No abstract text available
    Text: HXILINX Virtex 2,5 ¥ Field Programmable Gate Arrays N ovem ber 9, 1998 Version 1.1 - AD VAN C E P roduct S pecification Features • • • • • • Fast, high-density Field-P rogram m able Gate Arrays - D ensities from 50 k to 1M system gates - System perform ance up to 200 MHz


    OCR Scan     		PDF BG432 BG352 HQ240 FG600 FG680 XCV300-6PQ240C

    Untitled

    Abstract: No abstract text available
    Text: flX IU N X Spartan and S p artan X l Families Field Programmable Gate Arrays September 28, 1998 Version 1.2 Preliminary Product Specification Introduction • System level features - Available in both 5.0 Volt and 3.3 Volt versions - On-chip SelectRAM memory


    OCR Scan     		PDF SpartaXCS20XL-4 PQ208C PQ208

    Untitled

    Abstract: No abstract text available
    Text: Spartan and SpartanXL Families Field Programmable Gate Arrays £ XILINX January 6 , 1999 Version 1.4 Prelim inary Product Specification Introduction • The S partan Series is the first high-volum e production FPGA solution to deliver all the key requirem ents for ASIC


    OCR Scan     		PDF 5M-1994 M0-151-BAL-2