DP U1
Abstract: IO317 AX1000
Text: Advanced v1.5 Axcelerator Family FPGAs Leading-Edge Performance • • • • – Voltage-Referenced I/O Standards: GTL+, HSTL Class 1, SSTL2 Class 1 and 2, SSTL3 Class 1 and 2 – Registered I/Os with 64-bit Deep FIFO on Each Pin "PerPin FIFO" – Hot-Swap Compliant I/Os (Except PCI)
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Original
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700Mb/s
339kbits
DP U1
IO317
AX1000
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PDF
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AX1000
Abstract: No abstract text available
Text: Advanced v1.3 Axcelerator Family FPGAs Leading-Edge Performance • • • • – Voltage-Referenced I/O Standards: GTL+, HSTL Class 1, SSTL2 Class 1 and 2, SSTL3 Class 1 and 2 – Registered I/Os with 64-bit Deep FIFO on Each Pin "PerPin FIFO" – Hot-Swap Compliant I/Os (Except PCI)
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Original
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64-bit
608-bit
14tains
AX1000
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PDF
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AK 1022
Abstract: AF2.5 din 74 FIFO64K36 V123A AX1000
Text: Advanced v1.2 Axcelerator Family FPGAs Leading-Edge Performance • • • • – Voltage-Referenced I/O Standards: GTL+, HSTL Class 1, SSTL2 Class 1 and 2, SSTL3 Class 1 and 2 – Registered I/Os with 64-bit Deep FIFO on Each Pin "PerPin FIFO" – Hot-Swap Compliant I/Os (Except PCI)
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Original
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700Mb/s
339kbits
AK 1022
AF2.5 din 74
FIFO64K36
V123A
AX1000
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PDF
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v1493a
Abstract: AK 1022
Text: Advanced v1.4 Axcelerator Family FPGAs Leading-Edge Performance • • • • – Voltage-Referenced I/O Standards: GTL+, HSTL Class 1, SSTL2 Class 1 and 2, SSTL3 Class 1 and 2 – Registered I/Os with 64-bit Deep FIFO on Each Pin "PerPin FIFO" – Hot-Swap Compliant I/Os (Except PCI)
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Original
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700Mb/s
339kbits
v1493a
AK 1022
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PDF
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dunlop s 708
Abstract: PTI 30 040 ga AX125 AX2000 CS180 FG256 FG324 FG484 PQ208 M33 thermal fuse
Text: Advanced v1.5 Axcelerator Family FPGAs Le adi n g- E dg e P e rfo r ma nc e • • • • – Voltage-Referenced I/O Standards: GTL+, HSTL Class 1, SSTL2 Class 1 and 2, SSTL3 Class 1 and 2 – Registered I/Os with 64-bit Deep FIFO on Each Pin "PerPin FIFO"
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Original
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64-bit
608-bit
dunlop s 708
PTI 30 040 ga
AX125
AX2000
CS180
FG256
FG324
FG484
PQ208
M33 thermal fuse
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PDF
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SSTL-2
Abstract: BB1110B BB1110B13 BB1110B7 BB1110TB BB2110DI
Text: 4200 Bonita Place, Fullerton, CA 92635 BB1110TB, BB1110TB AND BB2110DI DDR SDRAM TERMINATOR NETWORKS. DESCRIPTION This “BB” family of networks is for terminating SSTL_2 Class I and Class II systems, such as DDR SDRAM. These specialty networks employ solder
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Original
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BB1110TB,
BB1110TB
BB2110DI
BB1110B13
BB1110B
BB1110TB
SSTL-2
BB1110B
BB1110B13
BB1110B7
BB2110DI
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PDF
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RT2404B7
Abstract: RT2460B7 RT2405B7 RT2400 CTS RESISTOR NETWORK 761 RT1400B7 RT2465B7 RT1400B6 RT1401B6 RT1401B7
Text: DDR SDRAM Terminator Technical Data Sheet RoHS Compliant Parts Available Description Features This SSTL_2 terminator network provides high performance resistor termination for SSTL_2 Class I or Class II systems. • • • • • • • Designed with a ceramic substrate, this device minimizes
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Original
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RT2404
RT2402
RT2404B7
RT2460B7
RT2405B7
RT2400
CTS RESISTOR NETWORK 761
RT1400B7
RT2465B7
RT1400B6
RT1401B6
RT1401B7
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PDF
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BB110B
Abstract: BB1110B BB1110B13 BB1110B7 BB2110DI TAPE AND REEL BGA
Text: 4200 Bonita Place, Fullerton, CA 92635 BB1110B AND BB2110DI -DDR SRAM TERMINATOR NETWORKS. DESCRIPTION The BB110B and BB2110DI are BGA Resistor Networks designed to terminate SSTL_2 Class I and Class II systems. These Networks use thick film resistors with high temperature solder balls. The resistors are integrated
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Original
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BB1110B
BB2110DI
BB110B
BB1110B
BB2110DI
13-inch
BB1110B7
BB1110B13
BB1110B13
BB1110B7
TAPE AND REEL BGA
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PDF
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SN74SSTL32877
Abstract: No abstract text available
Text: SN74SSTL32877 26-BIT REGISTERED BUFFER WITH SSTL_2 INPUTS AND OUTPUTS DESIGN GOAL DESIGN GOAL SCES241A – APRIL 1999 – REVISED MAY 1999 D Member of the Texas Instruments D D D D Differential CLK Signal D Meets SSTL_2 Class I and Class II Widebus Family
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Original
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SN74SSTL32877
26-BIT
SCES241A
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PDF
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SSTL
Abstract: BI-Tech double diode parallel BB1110B BB1110B13 BB1110B7 BB1110TB BB2110DI
Text: 4200 Bonita Place, Fullerton, CA 92635 BB1110TB, BB1110B AND BB2110DI DDR SDRAM TERMINATOR NETWORKS. DESCRIPTION This “BB” family of networks is for terminating SSTL_2 Class I and Class II systems, such as DDR SDRAM. These specialty networks employ solder balls for surface mount flip chip attachment. Their
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Original
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BB1110TB,
BB1110B
BB2110DI
BB1110B7
BB1110B13
BB1110B
SSTL
BI-Tech
double diode parallel
BB1110B13
BB1110B7
BB1110TB
BB2110DI
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PDF
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BB1110B7
Abstract: BB1110B13
Text: 4200 Bonita Place, Fullerton, CA 92635 BB1110B AND BB2110DI -DDR SRAM TERMINATOR NETWORKS. DESCRIPTION Networks are designed to terminate SSTL_2 Class I and Class II systems. Networks use thick film resistors with high temperature solder balls. With solder balls on resistor side no via connection and ceramic substrate
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Original
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BB1110B
BB2110DI
13-inch
BB1110B7
BB1110B13
BB1110B7
BB1110B13
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PDF
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ICSSSTV16857
Abstract: No abstract text available
Text: ICSSSTV16857 Integrated Circuit Systems, Inc. Preliminary Product Preview DDR 14-Bit Registered Buffer Recommended Application: DDR Memory Modules Product Features: • Differential clock signal • Meets SSTL_2 signal data • Supports SSTL_2 class I & II specifications
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Original
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ICSSSTV16857
14-Bit
MO-153
ICSSSTV16857yG-T
ICSSSTV16857
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PDF
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Untitled
Abstract: No abstract text available
Text: ICSSSTV16857 Integrated Circuit Systems, Inc. Preliminary Product Preview DDR 14-Bit Registered Buffer Recommended Application: DDR Memory Modules Product Features: • Differential clock signal • Meets SSTL_2 signal data • Supports SSTL_2 class I & II specifications
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Original
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ICSSSTV16857
14-Bit
MO-153
ICSSSTV16857y
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PDF
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ICSSSTV16857
Abstract: No abstract text available
Text: ICSSSTV16857 Integrated Circuit Systems, Inc. Preliminary Product Preview DDR 14-Bit Registered Buffer Recommended Application: DDR Memory Modules Product Features: • Differential clock signal • Meets SSTL_2 signal data • Supports SSTL_2 class I & II specifications
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Original
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ICSSSTV16857
14-Bit
MO-153
ICSSSTV16857yG-T
ICSSSTV16857
|
PDF
|
|
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ICSSSTV16857C
Abstract: No abstract text available
Text: Integrated Circuit Systems, Inc. ICSSSTV16857C DDR 14-Bit Registered Buffer Recommended Application: DDR Memory Modules Product Features: • Differential clock signal • Meets SSTL_2 signal data • Supports SSTL_2 class I & II specifications • Low-voltage operation
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Original
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ICSSSTV16857C
14-Bit
ICSSSTV16857CyL-T
ICSSSTV16857C
|
PDF
|
Untitled
Abstract: No abstract text available
Text: Integrated Circuit Systems, Inc. ICSSSTV16857 DDR 14-Bit Registered Buffer Recommended Application: DDR Memory Modules Product Features: • Differential clock signal • Meets SSTL_2 signal data • Supports SSTL_2 class I & II specifications • low-voltage operation
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Original
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ICSSSTV16857
14-Bit
SSTV16857CG
SSTV16857CGLF
PAG48)
SSTV16857CGLFT
SSTV16857CGT
SSTV16857C
TB-0510-05
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PDF
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Untitled
Abstract: No abstract text available
Text: Integrated Circuit Systems, Inc. ICSSSTV16857C DDR 14-Bit Registered Buffer Recommended Application: DDR Memory Modules Product Features: • Differential clock signal • Meets SSTL_2 signal data • Supports SSTL_2 class I & II specifications • low-voltage operation
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Original
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ICSSSTV16857C
14-Bit
ICSSSTV16857CyL-T
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PDF
|
Untitled
Abstract: No abstract text available
Text: Integrated Circuit Systems, Inc. ICSSSTV16857C DDR 14-Bit Registered Buffer Recommended Application: DDR Memory Modules Product Features: • Differential clock signal • Meets SSTL_2 signal data • Supports SSTL_2 class I & II specifications • Low-voltage operation
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Original
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ICSSSTV16857C
14-Bit
XSSTV16857CG
SSTV16857CGLF
PAG48)
SSTV16857CGLFT
SSTV16857CGT
SSTV16857C
TB-0510-05
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PDF
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ICSSSTV16857
Abstract: No abstract text available
Text: Integrated Circuit Systems, Inc. ICSSSTV16857 DDR 14-Bit Registered Buffer Recommended Application: DDR Memory Modules Product Features: • Differential clock signal • Meets SSTL_2 signal data • Supports SSTL_2 class I & II specifications • low-voltage operation
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Original
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ICSSSTV16857
14-Bit
ICSSSTV16857yL-T
ICSSSTV16857
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PDF
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KM416S4031BT-G8
Abstract: No abstract text available
Text: KM416S4031B CMOS SDRAM 1M x 16Bit x 4 Banks Synchronous DRAM with SSTL interface FEATURES GENERAL DESCRIPTION •JEDEC standard 3.3V power supply •SSTL_3 Class II compatible with multiplexed address •Four banks operation •MRS cycle with address key programs
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Original
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KM416S4031B
16Bit
KM416S4031B
A10/AP
KM416S4031BT-G8
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PDF
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KM416S4030AT
Abstract: ZX-03 KM416S4030AT-G
Text: KM416S4030AT SDRAM ELECTRONICS 1M x 16Bitx 4 Bank Synchronous DRAM FEATURES GENERAL DESCRIPTION • JEDEC standard 3.3V Power Supply. • LVTTL/SSTL_3 Class II compatible with multiplexed address. • 4 banks operation. • MRS cycle with address key programs.
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OCR Scan
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KM416S4030AT
16Bitx
KM416S4030A/KM416S4031A
KM416S4030AT)
KM416S4030AT
ZX-03
KM416S4030AT-G
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PDF
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Untitled
Abstract: No abstract text available
Text: KM416S1020BT SDRAM ELECTRONICS 512K x 16B itx2 Bank Synchronous DRAM FEATURES GENERAL DESCRIPTION • JEDEC standard 3.3V Power Supply. • LVTTL/SSTL_3 Class II compatible with multiplexed address. • Dual banks operation. • MRS cycle with address key programs.
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OCR Scan
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KM416S1020BT
KM416S1020B/KM416S1021B
50-TSOP2-400F
50-TSOP2-400R
D03b2b2
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PDF
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KM416S4020
Abstract: KM416S4020AT-G
Text: KM416S4020AT SDRAM ELECTRONICS 2M x 16Bitx 2 Bank Synchronous DRAM FEATURES GENERAL DESCRIPTION • JEDEC standard 3.3V Power Supply. • LVTTL/SSTL_3 Class II compatible with multiplexed address. • Dual banks operation. • MRS cycle with address key programs.
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OCR Scan
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KM416S4020AT
16Bitx
KM416S4020A/KM416S4021A
KM416S4020AT)
0D33D5S
KM416S4020
KM416S4020AT-G
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PDF
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Untitled
Abstract: No abstract text available
Text: Preliminary KM416S1021C CMOS SDRAM 512Kx 16Bitx 2 Banks Synchronous DRAM with SSTL interface FEATURES GENERAL DESCRIPTION • JEDEC standard 3.3V power supply > SSTL_3 Class II compatible with multiplexed address • Dual banks operation • MRS cycle with address key programs
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OCR Scan
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KM416S1021C
512Kx
16Bitx
KM416S1021C
10/AP
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PDF
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