Untitled
Abstract: No abstract text available
Text: Preliminary Revised O ctob e r 1998 SEMICONDUCTOR TM NC7SZ175 TinyLogic UHS D-Type Flip-Flop with Asynchronous Clear Preliminary General Description A LOW input to C lear sets th e Q output to LO W level. The C lear input is independent o f clock. The N C 7SZ175 is a single positive edge-triggered D-type
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NC7SZ175
7SZ175
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Untitled
Abstract: No abstract text available
Text: Revised February 1999 EMICONDUCTGRTM MM74HC164 8-Bit Serial-in/Parallel-out Shift Register tion of the clock pulse. C lear is independent of th e clock and accom plished by a low level at th e C LEAR input. General Description The M M 74H C 164 utilizes advanced silicon-gate C M OS
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MM74HC164
MM74HC164
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Untitled
Abstract: No abstract text available
Text: Preliminary SEMICONDUCTOR Revised S eptem ber 1998 TM NC7SZ175 TinyLogic UHS D-Type Flip-Flop with Asynchronous Clear Preliminary General Description A LOW input to C lear sets th e Q output to LO W level. The C lear input is independent o f clock. The N C 7SZ175 is a single positive edge-triggered D-type
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NC7SZ175
7SZ175
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74HC164M
Abstract: 74HC164N 74HC164N PIN DIAGRAM M74HC164n MM74HC164N
Text: Revised February 1999 SEMICONDUCTOR TM MM74HC164 8-Bit Serial-in/Parallel-out Shift Register tion of the clock pulse. C lear is independent of th e clock and accom plished by a low level a t th e C LEAR input. General Description The M M 74H C 164 utilizes advanced silicon-gate CM OS
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MM74HC164
74HC164M
74HC164N
74HC164N PIN DIAGRAM
M74HC164n
MM74HC164N
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Untitled
Abstract: No abstract text available
Text: Prelim inary Revised S eptem ber 1998 E M I C D N D U C T O R tm NC7SZ175 TinyLogic UHS D-Type Flip-Flop with Asynchronous Clear Preliminary A LOW input to C lear sets th e Q output to LOW level. The C lear input is independent o f clock. • S pace saving SC 70 6-lead package
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NC7SZ175
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C7SZ175
Abstract: 7SZ175
Text: Revised January 1999 S E M I C O N D U C T O R TM NC7SZ175 TinyLogic UHS D-Type Flip-Flop with Asynchronous Clear LOW input to C lear sets the Q output to LOW level. The C lear input is independent o f clock. • S pace saving SC 70 6-lead package device is specified to operate over the 1 .8 V to 5 .5 V V q q
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NC7SZ175
C7SZ175
7SZ175
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042J
Abstract: NC7SZ175 NC7SZ175P6 NC7SZ175P6X SC70-6
Text: Revised April 1999 S E M I C O N D U C T O R TM NC7SZ175 TinyLogic UHS D-Type Flip-Flop with Asynchronous Clear LO W input to C lear sets the Q output to LO W level. The C lear input is independent of clock. • S pace saving S C 70 6-lead package device is specified to operate over th e 1.8V to 5 .5V V qq
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NC7SZ175
NC7SZ175
042J
NC7SZ175P6
NC7SZ175P6X
SC70-6
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TLYE260AKL
Abstract: No abstract text available
Text: TOSHIBA TLYE260A TOSHIBA LED LAMP PANEL CIRCUIT INDICATOR InGaAfP YELLOW LIGHT EMISSION TLYE260A 3.0mm DIAMETER In G aA iP YELLOW LED All Plastic Mold Type. Colorless C lear Lens Low Drive Current, High Intensity Yellow Light Em ission Recommended Forward Current : lF = 15~20m A DC
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TLYE260A
18-36mcd,
32-64mcd,
56-112mcd.
TLYE260AKL
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Untitled
Abstract: No abstract text available
Text: Revised March 1999 SEMICONDUCTOR TM 74LVX74 Low Voltage Dual D-Type Positive Edge-Triggered Flip-Flop General Description A synchronous Inputs: The LVX74 is a dual D-type flip-flop with Asynchronous C lear and S e t inputs and com plem entary Q, Q outputs.
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74LVX74
LVX74
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Untitled
Abstract: No abstract text available
Text: THIS DRAWING IS UNPUBLISHED. COPYRIGHT RELEASED FOR PUBLICATION BY TYCO ELECTRONICS CORPORATION. SUGGESTED ALL RIGHTS RESERVED. M A T IN G S H O U L D E R MAY BE F NOT FEASIBLE D 10 .46 M IN DIST AF 50 REVISIONS LTR i512H C LEAR AN C E 1.02 0*76 0.25 .040
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16JUN03
i512H
31MAR2000
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9606
Abstract: 9719
Text: 2ôl2b72 Q0047b5 5b2 2mm X 4mm Discrete LED Dîalîght Standard Efficiency Tinted 521-9606, -9607, -9658, -9719 a 93 I.JS7] t 2.54 J [.100 PART NO. LED COLOR 521-9606 521-9607 521-9658 521-9719 G reen Diffused Yellow Diffused Red Diffused Blue C lear ._
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l2b72
Q0047b5
From50
From25Â
MIL-STD-202E,
100mA
9606
9719
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TLGA262
Abstract: No abstract text available
Text: TOSHIBA TLGA262 TENTATIVE TOSHIBA LED LAMP PANEL CIRCUIT INDICATOR • 3mm DIAM ETER T l-3 /4 • InGaA^P G R EEN LED • A ll Plastic Mold Type. • Colorless C lear Lens InGaA^P GREEN LIGHT EMISSION TLGA262 • Low Drive Current, High Intensity Green Light Em ission
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TLGA262
TLGA262
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521-9720
Abstract: No abstract text available
Text: Sfil2b72 0 0 0 4 7 ^ 1Q6 2mm x 7mm Discrete LED Rectangular Tinted, Diffused 521 -9264, Dîalîght -9265, -9266, -9720 u s PART NO. 521-9264 LED COLOR i :] 521-9265 521-9266 521-9720 Yellow Diffused 2.41 [.095] r 2.54 |[-100] Red Diffused Green Diffused Blue C lear
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2fll2b72
10fjs
M1L-STD-202E,
100pA
521-9720
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74ACTQ823
Abstract: M24B N24C
Text: April 1993 74ACTQ823 Quiet Series 9-Bit D Flip-Flop with TRI-STATE Outputs General Description Features The ’A C TQ 823 is a 9-bit buffered register. It features Clock Enable and C lear which are ideal fo r parity bus interfacing in high perform ance m icroprogram m ing
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74ACTQ823
ACTQ823
74ACTQ823
M24B
N24C
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Untitled
Abstract: No abstract text available
Text: ^a rc h "f., jQ Q Q Revised April 1999 74LCX74 Low Voltage Dual D-Type Positive Edge-Triggered Flip-Flop with 5V Tolerant Inputs General Description Features T h e LCX74 is a dual D -type flip-flop with Asynchronous C lear and Set inputs and com plem entary Q, Q outputs.
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74LCX74
LCX74
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Untitled
Abstract: No abstract text available
Text: January 1988 M M 54H C 174/M M 74H C 174 Hex D Flip-Flops w ith C lear General Description Features These edge triggered flip-flops utilize advanced silicon-gate CMOS technology to implement D-type flip-flops. They pos sess high noise immunity, low power, and speeds compara
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174/M
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D406
Abstract: 74F114 74F114PC 74F114SC F114 M14A N14A
Text: S E M IC O N D U C T O R tm 74F114 Dual JK Negative Edge-Triggered Flip-Flop with Common Clocks and Clears A synchronous Inputs: General Description The ’F114 contains tw o high-speed JK flip-flops w ith com mon Clock and C lear inputs. Synchronous state changes are
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74F114
D406
74F114
74F114PC
74F114SC
F114
M14A
N14A
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and pin diagram of IC 7491
Abstract: No abstract text available
Text: February 1999 Semiconductor 54A C T825 8-Bit D Flip-Flop General Description Features The ’A C T 825 is an 8-bit buffered register. They have C lock Enable and C lear features w hich are ideal fo r parity bus in terfacing in high perform ance m icroprogram m ing system s.
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54ACT825
and pin diagram of IC 7491
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Untitled
Abstract: No abstract text available
Text: January 1988 M M 54H C 175/M M 74H C 175 Quad D -Type Flip-Flop W ith C lear General Description This high speed D-TYPE FLIP-FLOP with complementary outputs utilizes advanced silicon-gate CMOS technology to achieve the high noise immunity and low power consump
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175/M
MM54HC175/
MM74HC175
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Untitled
Abstract: No abstract text available
Text: 74AC74 • 74ACT74 Dual D-Type Positive Edge-Triggered Flip-Flop General Description A synchronous Inputs: The A C /AC T74 is a dual D-type flip-flop with Asynchronous C lear and S e t inputs and com plem entary Q, Q outputs. Inform ation at the input is transferred to the outputs on the
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74AC74
74ACT74
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Untitled
Abstract: No abstract text available
Text: E M IC O N D U C T O R T 74F114 Dual JK Negative Edge-Triggered Flip-Flop with Common Clocks and Clears General Description A synchronous Inputs: The ’F114 contains tw o high-speed JK flip-flops with com mon C lock and C lear inputs. Synchronous state changes are
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74F114
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54ACT
Abstract: J24F M24B N24C W24C
Text: March 1993 54ACT/74 ACT825 8-Bit D Flip-Flop General Description Features The ’A C T825 is an 8 -bit buffered register. T h e y have Clock Enable and C lear fe a tu re s w hich are ideal fo r parity bus interfacing in high perform ance m icroprogram m ing system s.
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54ACT/74ACT825
ACT825
Am29825
ACT825:
54ACT
J24F
M24B
N24C
W24C
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LVX74
Abstract: 74LVX74 74LVX74M 74LVX74MTC 74LVX74SJ M14A M14D MTC14 E738
Text: S E M I C O N D U C T O R Revised M arch 1999 TM A synchronous Inputs: General Description The LVX74 is a dual D -type flip-flop with Asynchronous C lear and Set inputs and com plem entary Q, Q outputs. Inform ation at the input is transferred to the outputs on the
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74LVX74
LVX74
74LVX74
74LVX74M
74LVX74MTC
74LVX74SJ
M14A
M14D
MTC14
E738
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64 CERAMIC LEADLESS CHIP CARRIER LCC
Abstract: 54F823FM 54F823LM 54F823SDM 74F823 74F823SC 74F823SPC J24F M24B N24C
Text: S E M IC O N D U C T O R tm 74F823 9-Bit D-Type Flip-Flop General Description Features The ’F823 Is a 9-bit buffered register. It features C lock En able and C lear w hich are ideal for parity bus interfacing in high perform ance m icroprogram m ing systems.
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74F823
Am29823
74F823SPC
24-Lead
54F823SDM
74F823SC
54F823FM
64 CERAMIC LEADLESS CHIP CARRIER LCC
54F823FM
54F823LM
54F823SDM
74F823
74F823SC
74F823SPC
J24F
M24B
N24C
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