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    PLCC 52 PIN CONFIGURATION Search Results

    PLCC 52 PIN CONFIGURATION Result Highlights (5)

    Part ECAD Model Manufacturer Description Download Buy
    CS-DSDMDB09MF-010 Amphenol Cables on Demand Amphenol CS-DSDMDB09MF-010 9-Pin (DB9) Deluxe D-Sub Cable - Copper Shielded - Male / Female 10ft Datasheet
    CS-DSDMDB15MF-002.5 Amphenol Cables on Demand Amphenol CS-DSDMDB15MF-002.5 15-Pin (DB15) Deluxe D-Sub Cable - Copper Shielded - Male / Female 2.5ft Datasheet
    CS-DSDMDB15MM-025 Amphenol Cables on Demand Amphenol CS-DSDMDB15MM-025 15-Pin (DB15) Deluxe D-Sub Cable - Copper Shielded - Male / Male 25ft Datasheet
    CS-DSDMDB25MM-010 Amphenol Cables on Demand Amphenol CS-DSDMDB25MM-010 25-Pin (DB25) Deluxe D-Sub Cable - Copper Shielded - Male / Male 10ft Datasheet
    CS-DSDMDB37MM-002.5 Amphenol Cables on Demand Amphenol CS-DSDMDB37MM-002.5 37-Pin (DB37) Deluxe D-Sub Cable - Copper Shielded - Male / Male 2.5ft Datasheet

    PLCC 52 PIN CONFIGURATION Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    C4558

    Abstract: c455 CY7C447 C4557 C4556 CY7C455 CY7C456 CY7C457 CY7C455-20JC
    Text: 57 CY7C455 CY7C456 CY7C457 512 x 18, 1K x 18, and 2K x 18 Cascadable Clocked FIFOs with Programmable Flags Features • Depth Expansion Capability • 52-pin PLCC and 52-pin PQFP • High-speed, low-power, first-in first-out FIFO memories • 512 x 18 (CY7C455)


    Original     		PDF CY7C455 CY7C456 CY7C457 52-pin CY7C455) CY7C456) CY7C457) 83-MHz C4558 c455 CY7C447 C4557 C4556 CY7C455 CY7C456 CY7C457 CY7C455-20JC

    C4558

    Abstract: C4554 C4557 c455 CY7C455-14JI CY7C455 CY7C456 CY7C457 CY7C447
    Text: CY7C455 CY7C456 CY7C457 512 x 18, 1K x 18, and 2K x 18 Cascadable Clocked FIFOs with Programmable Flags • Depth Expansion Capability • 52-pin PLCC and 52-pin PQFP Features • High-speed, low-power, first-in first-out FIFO memories • 512 x 18 (CY7C455)


    Original     		PDF CY7C455 CY7C456 CY7C457 52-pin CY7C455) CY7C456) CY7C457) 83-MHz C4558 C4554 C4557 c455 CY7C455-14JI CY7C455 CY7C456 CY7C457 CY7C447

    C4558

    Abstract: c455 CY7C455 CY7C456 CY7C457 CY7C447
    Text: 57 CY7C455 CY7C456 CY7C457 512 x 18, 1K x 18, and 2K x 18 Cascadable Clocked FIFOs with Programmable Flags Features • Depth Expansion Capability • 52-pin PLCC and 52-pin PQFP • High-speed, low-power, first-in first-out FIFO memories • 512 x 18 (CY7C455)


    Original     		PDF CY7C455 CY7C456 CY7C457 52-pin CY7C455) CY7C456) CY7C457) 83-MHz C4558 c455 CY7C455 CY7C456 CY7C457 CY7C447

    C4558

    Abstract: C4557 c4552 C4555 c4556 C-4555 c4554 c455 CY7C455 CY7C457
    Text: 57 CY7C455 CY7C456 CY7C457 512 x 18, 1K x 18, and 2K x 18 Cascadable Clocked FIFOs with Programmable Flags Features • Depth Expansion Capability • 52-pin PLCC and 52-pin PQFP • High-speed, low-power, first-in first-out FIFO memories • 512 x 18 (CY7C455)


    Original     		PDF CY7C455 CY7C456 CY7C457 52-pin CY7C455) CY7C456) CY7C457) 83-MHz C4558 C4557 c4552 C4555 c4556 C-4555 c4554 c455 CY7C455 CY7C457

    CY7C342

    Abstract: of 7400 Series TTL TTL 7400 cmos logic 7400 series
    Text: 42 CY7C342 128-Macrocell MAX EPLD Features • • • • • 128 macrocells in 8 LABs 8 dedicated inputs, 52 bidirectional I/O pins Programmable interconnect array 0.8-micron double-metal CMOS EPROM technology Available in 68-pin HLCC, PLCC, and PGA packages


    Original     		PDF CY7C342 128-Macrocell 68-pin CY7C342 of 7400 Series TTL TTL 7400 cmos logic 7400 series

    Untitled

    Abstract: No abstract text available
    Text: Accutek Microcircuit Corporation DESCRIPTION The Accutek family of AccuPGA Adapter Modules are designed to permit the soldering of surface mount PLCC devices into a standard PGA through-hole PC board. These AccuPGA modules are a pin compatible drop in replacement for end-of-life PGA devices. Standard pin counts include 28, 32, 44, 52, 68, 84 and 100 pins. Can accommodate square and rectangular PLCCs with 0.050” lead pitch


    Original     		PDF AK84PLCC-PGA AK68PLCC-PGA AK52PLCC-PGA AK52PLCC-PGA AK44PLCC-PGA AK32PLCC-PGA AK28PLCC-PGA AK44PLCC-PGA AK32PLCC-PGA

    Untitled

    Abstract: No abstract text available
    Text: A Sockets for IC-PLCC PLCC sockets for case design EIA/JEDEC TYPE "A" VPE = packing unit pieces/tube data sheet for pin configuration of individual PLCC sockets available upon request dual polarity indicators guarantee the correct alignment of the chip drainage holes for easier inside cleaning


    Original     		PDF

    microcontroller 8051 application of alarm clock

    Abstract: 80C52 DS83C530 DS83C530-QCL DS87C530 DS87C530-ECL DS87C530-ENL DS87C530-KCL DS87C530-QCL DS87C530-QNL
    Text: DS87C530/DS83C530 EPROM/ROM Microcontrollers with Real-Time Clock www.maxim-ic.com FEATURES § PIN CONFIGURATIONS 80C52 Compatible 8051 Instruction-Set Compatible Four 8-Bit I/O Ports Three 16-Bit Timer/Counters 256 Bytes Scratchpad RAM § Large On-Chip Memory


    Original     		PDF DS87C530/DS83C530 80C52 16-Bit DS87C530 DS83C530 DS87C530 DS87C530, DS83C530, DS87C530/DS83C530 microcontroller 8051 application of alarm clock DS83C530 DS83C530-QCL DS87C530-ECL DS87C530-ENL DS87C530-KCL DS87C530-QCL DS87C530-QNL

    AT17F040

    Abstract: AT17F080 AT24CXXX AT40K AT94K ATDH2200E XC3000 XC4000 XC5200
    Text: Features • Programmable 4,194,304 x 1 and 8,388,608 x 1-bit Serial Memories Designed to Store Configuration Programs for Field Programmable Gate Arrays FPGAs • 3.3V Output Capability • 5V Tolerant I/O Pins • Program Support using the Atmel ATDH2200E System or Industry Third Party


    Original     		PDF ATDH2200E AT40K AT94K XC3000, XC4000, XC5200, MPA1000 3039J AT17F040 AT17F080 AT24CXXX XC3000 XC4000 XC5200

    i1991

    Abstract: 11991
    Text: ADVANCE l^ iic n o N MT5C2516 LATCHED SRAM 16K x 16 SRAM WITH ADDRESS/ DATA INPUT LATCHES FEATURES • • • • OPTIONS MARKING • Timing 15ns access 17ns access 20ns access 25ns access -15 -17 -20 -25 • Packages 52-pin PLCC 52-pin PQFP EJ LG 52-Pin PLCC D-3


    OCR Scan     		PDF MT5C2516 52-Pin T1991 i1991 11991

    LT 5251

    Abstract: DP2 marking
    Text: MT5C2818 16K X 18 L A T C H E D S R A M |U |C Z R O N 16K X 18 SRAM LATCHED SRAM WITH ADDRESS/ DATA INPUT LATCHES FEATURES • • • • OPTIONS 52-Pin PLCC SC-2 52-Pin PQFP (SC-5) S =1111 SB s s m ÏÏIUJ < <lolcDI£D > > 15 < I o 5 4 3 2 Packages 52-pin PLCC


    OCR Scan     		PDF MT5C2818 52-Pin MT5C2816 LT 5251 DP2 marking

    Untitled

    Abstract: No abstract text available
    Text: p iC R ü N 16K LATCHED SRAM X MT5C2818 18 LATCHED SRAM 16K X 18 SRAM WITH ADDRESS/ DATA INPUT LATCHES FEATURES OPTIONS MARKING • Timing 12ns access 15ns access 20ns access 25ns access -12 -15 -20 -25 Packages 52-pin PLCC 52-pin PQFP PIN ASSIGNMENT Top View


    OCR Scan     		PDF MT5C2818 52-Pin MT5C2816

    Untitled

    Abstract: No abstract text available
    Text: M IC R O N 16K LATCHED SRAM X MT5C2516 16 LATCHED SRAM 16K x 16 SRAM WITH ADDRESS/ DATA INPUT LATCHES FEATURES • • • • PIN ASSIGNMENT (Top View 52-Pin PLCC (SC-2) 52-Pin PQFP (SC-5) 2 - in illl? OPTIONS MARKING • Timing 12ns access 15ns access


    OCR Scan     		PDF MT5C2516 52-Pin MT5C2516EJ-20

    11991

    Abstract: No abstract text available
    Text: ADVANCE p ilC R O N MT5C2818 LATCHED SRAM 16K x 18 SRAM WITH ADDRESS/ ADDRESS/ WITH DATA INPUT LATCHES FEATURES • • • • 52-Pin PLCC D-3 52-Pin PQFP (D-5) OPTIONS MARKING • Timing 15ns access 17ns access 20ns access 25ns access -15 -17 -20 -25 DQ6


    OCR Scan     		PDF MT5C2818 52-Pin T5C2818 MT5C2918 11991

    MT5C2516

    Abstract: No abstract text available
    Text: MT5C2516 16K X 16 LA T C H E D SRAM MICRON 16K x 16 SRAM LATCHED SRAM WITH ADDRESS/ DATA INPUT LATCHES FEATURES • • • • 52-Pin PLCC SC-2 52-Pin PQFP (SC-5) ! - H S 5 8 KM “ iuj £ ui : <loim lm > >13 < !o < < o OPTIONS MARKING • Timing 12ns access


    OCR Scan     		PDF MT5C2516 52-Pin MT5C2S16

    CY7C342B-25HMB

    Abstract: CY7C342B-35HMB 68-PIN CY7C342B 415l
    Text: # CYPRESS Features • 128 macrocells in 8 LABs • 8 dedicated inputs, 52 bidirectional I/O pins • Programmable interconnect array • Advanced 0.65-micron CMOS technology to increase performance • Available in 68-pin HLCC, PLCC, and PGA Functional Description


    OCR Scan     		PDF CY7C342B 128-Macrocell 65-micron 68-pin CY7C342B 35HMB CY7C342Bâ 35RMB CY7C342B-25HMB CY7C342B-35HMB 415l

    EQUIVALENT cd 1031 cs

    Abstract: 7C1031
    Text: CY7C1031 CY7C1032 PRELIM INARY 64K x 18 Synchronous Cache RAM • Direct interface with the processor and external cache controller • Asynchronous output enable • VOs capable of 33V operation • JEDEC-standard pinout • 52-pin PLCC and PQFP packaging


    OCR Scan     		PDF CY7C1031 CY7C1032 66-MHz 7C1031) 7C1032) 52-pin EQUIVALENT cd 1031 cs 7C1031

    D1-D16

    Abstract: No abstract text available
    Text: PRELIMINARY M T56C 16K 16B 2 16K X 16 L A T C H E D S R A M |U |IC = R O N LATCHED SRAM 16K X 16 SRAM WITH ADDRESS/ DATA INPUT LATCHES, BYTE ENABLES FEATURES • • • • • • • OPTIONS 52-Pin PLCC SC-2 52-Pin PQFP (SC-5) S e m iti 8 < <!olcûlcü > >15 < IO < < o


    OCR Scan     		PDF 386SL MT56C16K16B2 D1-D16

    Untitled

    Abstract: No abstract text available
    Text: CY7C342 CY7C342B CYPRESS SEMICONDUCTOR & 128-Macrocell M A X EPLDs Features Functional Description • 128 macrocells in 8 LABs • 8 dedicated inputs, 52 bidirectional I/O pins • Programmable interconnect array • Available in 68-pin HLCC, PLCC, PGA, and Flatpack


    OCR Scan     		PDF CY7C342 CY7C342B 128-Macrocell 68-pin CY7C342/CY7C342B CY7C342/ CY7C342B Y7C342B

    Untitled

    Abstract: No abstract text available
    Text: CY7C1331 CY7C1332 ADVANCED INFORMATION 64K x 18 Synchronous Cache 3.3 V RAM Direct interface with the processor and external cache controller Asynchronous output enable JEDEC-standard pinout 52-pin PLCC and PQFP packaging Features • Supports 66-MHz Pentium proces­


    OCR Scan     		PDF CY7C1331 CY7C1332 66-MHz 7C1331) 7C1332) 52-pin

    Untitled

    Abstract: No abstract text available
    Text: QS88180, Q QS88160 High-Speed CMOS Dual 4Kx16/18 SRAM with Latched Addresses QS88180 QS88160 FEATURES/BENEFITS • Dual 4Kx18/16 allows 2-way set associative cache • Byte enables for byte/word read/write • 20ns/25 ns/30ns/35 ns Taa • Available in 52-pin PLCC


    OCR Scan     		PDF QS88180, QS88160 4Kx16/18 QS88180 4Kx18/16 20ns/25 ns/30ns/35 52-pin 16-bit

    Untitled

    Abstract: No abstract text available
    Text: QS88180, Q QS88160 High-Speed CMOS Dual 4Kx16/18 SRAM with Latched Addresses QS88180 QS88160 FEATURES/BENEFITS • • • • Dual 4Kx18/16 allows 2-way set associative cache Byte enables for byte/Word read/write 20ns/25 ns/30ns/35 ns Taa Available in 52-pin PLCC


    OCR Scan     		PDF QS88180, QS88160 4Kx16/18 QS88180 4Kx18/16 20ns/25 ns/30ns/35 52-pin 16-bit

    Untitled

    Abstract: No abstract text available
    Text: CYPRESS SEMICONDUCTOR 4bE D B 2 5 0 ^ 2 'T 't- l l y - I V 0007103 T I ICYP 0*7 CY7C342 CYPRESS ß r SEMICONDUCTOR • 128 macrocells in 8 LABs • 8 dedicated inputs, 52 bidirectional I/O pins • Programmable interconnect array • Available in 68-pin HLCC, PLCC,


    OCR Scan     		PDF CY7C342 68-pin CY7C342 7400-series 00G7120 tAC02 38-00119-B

    ys 2103

    Abstract: hex to 7 segment decoder CY7C132 CY7C146 CY7C136
    Text: CYPRESS S EMI COND UCTOR MbE D □ 5S0^bb2 GDDb 3S 3 7 C CYP CY7C132/CY7C136 CY7C142/CY7C146 2048 x 8 Dual-Port Static RAM output enable OE . BUSY flags are pro­ vided on each port. In addition, an interrupt flag (INT) is provided on each port of the 52-pin LCC and PLCC versions. BUSY sig­


    OCR Scan     		PDF 000l3s3 CY7C132/CY7C136 CY7C142/CY7C146 CY7C132/ CY7C136; 52-pin CY7C132/CY7C136/CY7C142/ ys 2103 hex to 7 segment decoder CY7C132 CY7C146 CY7C136