7b45
Abstract: schematic diagram of phone charger sot-23 marking YA Lithium-Ion Battery Charger sot 23 mark py sot IRF7805 SC1437 2sc1437 SOT23-5 marking par
Text: SC1437 Precision Voltage Detector With Programmable Trigger Voltage & Timer Delay POWER MANAGEMENT Description Features Low quiescent current, less than 10µA typical Input voltage range 1.8V to 6.8V Adjustable or preset voltage trip point Selectable timer delays of 0, 40 and 80ms without use of
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SC1437
OT-23
SC1437
20ms/div
OT23-5
7b45
schematic diagram of phone charger
sot-23 marking YA
Lithium-Ion Battery Charger sot 23
mark py sot
IRF7805
2sc1437
SOT23-5 marking par
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0-15 minutes timer
Abstract: 50hz bcd clock minutes seconds 50hz 100hz generator 24hr clock circuit KKA8583N alarm clock IC circuit of alarm clock
Text: TECHNICAL DATA CMOS timer with RAM and I2C-bus control. KKA8583N KKA8583N is a timer with RAM and I2C-bus control. Designed for use in appliances having I2C-bus as clock/calendar/timer/alarm/events counter for turning on functions of the appliance at preset time or upon completion of an
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KKA8583N
KKA8583N
OperatinKA8583
001BA)
0-15 minutes timer
50hz bcd clock minutes seconds
50hz 100hz generator
24hr clock circuit
alarm clock IC
circuit of alarm clock
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INA8583
Abstract: Ina8583n 50hz 100hz generator alarm clock by ic oscillator 32,768KHz 5V alarm clock IC
Text: TECHNICAL DATA CMOS timer with RAM and I2C-bus control. INA8583N INA8583N is a timer with RAM and I2C-bus control. Designed for use in appliances having I2C-bus as clock/calendar/timer/alarm/events counter for turning on functions of the appliance at preset time or upon completion of an
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INA8583N
INA8583N
OperatinNA8583
001BA)
INA8583
50hz 100hz generator
alarm clock by ic
oscillator 32,768KHz 5V
alarm clock IC
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WIDE BUS FAMILY
Abstract: No abstract text available
Text: Quantum38K ISR™ CPLD Family PRELIMINARY CPLDs at ASIC Prices™ Features • High density — 15K to 100K usable gates — 256 to 1536 macrocells — 92 to 302 maximum I/O pins — 8 Dedicated Inputs including 4 clock pins and 4 global control signal pins; 4 JTAG interface pins for
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Quantum38KTM
WIDE BUS FAMILY
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Untitled
Abstract: No abstract text available
Text: Quantum38K ISR™ CPLD Family PRELIMINARY CPLDs at ASIC Prices™ Features • High density — 30K to 100K usable gates — 512 to 1536 macrocells — 136 to 302 maximum I/O pins — 8 Dedicated Inputs including 4 clock pins and 4 global I/O control signal pins; 4 JTAG interface pins
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Quantum38KTM
38K15
144FBGA
MIL-STD-883"
/JESD22-A114-A
83MHz
66MHz"
125MHz
83MHz"
Quantum38K
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Untitled
Abstract: No abstract text available
Text: ISL45024 Data Sheet January 2004 256-Tap Quad-Channel Non-Volatile Digital Potentiometer FN6070 Features • 256 taps for each potentiometer The ISL45024 is a 256-tap, quad-channel non-volatile digital potentiometer available in 10kΩ, 50kΩ and 100kΩ end-to-end
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ISL45024
256-Tap
FN6070
ISL45024
256-tap,
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Untitled
Abstract: No abstract text available
Text: ISL45024 Data Sheet 256-Tap Quad-Channel Non-Volatile Digital Potentiometer The iPot ISL45024 DCP is a 256-tap, quad-channel non-volatile digital potentiometer available in 10kΩ, 50kΩ and 100kΩ end-to-end resistances. These devices can be used
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ISL45024
FN6070
256-Tap
ISL45024
256-tap,
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AEH 5PIN
Abstract: MAX8510 MAX8511 MAX8512 MAX8512EXK-T SC70-5
Text: 19-2732; Rev 0; 1/03 KIT ATION EVALU LE B A IL A AV Ultra-Low-Noise, High PSRR, Low-Dropout,120mA Linear Regulators in SC70 Features ♦ Space-Saving 5-Pin SC70 Package ♦ 11µVRMS Output Noise at 100Hz to 100kHz Bandwidth MAX8510 ♦ 78dB PSRR at 1kHz (MAX8510)
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120mA
100Hz
100kHz
MAX8510)
120mV
MAX8511)
MAX8510/MAX8511
AEH 5PIN
MAX8510
MAX8511
MAX8512
MAX8512EXK-T
SC70-5
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F100K
Abstract: SY100S336 SY100S336A SY100S336AFC SY100S336AJC SY100S336AJCTR
Text: ENHANCED 4-STAGE COUNTER/SHIFT REGISTER FEATURES DESCRIPTION • Max. shift frequency of 700MHz ■ Clock to Q delay max. of 1100ps ■ Sn to TC speed improved by 50% ■ Sn set-up and hold time reduced by more than 50% ■ IEE min. of –170mA ■ Industry standard 100K ECL levels
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700MHz
1100ps
170mA
F100K
24-pin
28-pin
SY100S336A
SY100S336,
SY100S336AJC
J28-1
F100K
SY100S336
SY100S336AFC
SY100S336AJC
SY100S336AJCTR
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SY100S336
Abstract: SY100S336A SY100S336AFC SY100S336AJC SY100S336AJCTR F100K
Text: ENHANCED 4-STAGE COUNTER/SHIFT REGISTER FEATURES DESCRIPTION • Max. shift frequency of 700MHz ■ Clock to Q delay max. of 1100ps ■ Sn to TC speed improved by 50% ■ Sn set-up and hold time reduced by more than 50% ■ IEE min. of –170mA ■ Industry standard 100K ECL levels
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700MHz
1100ps
170mA
F100K
24-pin
28-pin
SY100S336A
SY100S336,
SY100S336AJC
J28-1
SY100S336
SY100S336AFC
SY100S336AJC
SY100S336AJCTR
F100K
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MAX8510
Abstract: MAX8511 MAX8512 SC70-5 AEH 5PIN amplifier - ATH top mark
Text: 19-2732; Rev 4; 8/11 Ultra-Low-Noise, High PSRR, Low-Dropout, 120mA Linear Regulators Features ♦ Space-Saving SC70 and TDFN 2mm x 2mm Packages ♦ 11µVRMS Output Noise at 100Hz to 100kHz Bandwidth (MAX8510) ♦ 78dB PSRR at 1kHz (MAX8510) ♦ 120mV Dropout at 120mA Load
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120mA
100Hz
100kHz
MAX8510)
120mV
MAX8511)
MAX8510/MAX8511)
MAX8510
MAX8511
MAX8512
SC70-5
AEH 5PIN
amplifier - ATH top mark
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38K30
Abstract: DELTA39K
Text: USE DELTA39K FOR Quantum38K™ ISR™ ALL NEW DESIGNS CPLD Family CPLDs Designed for Migration Features • High density — 30K to 100K usable gates — 512 to 1536 macrocells — 136 to 302 maximum I/O pins — Eight dedicated inputs including four clock pins and
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DELTA39KTM
Quantum38KTM
16-Kb
48-Kb
125-MHz
18-mm
Quantum38K30
Quantum38K50
Quantum38K
Delta39K
38K30
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Untitled
Abstract: No abstract text available
Text: 19-2732; Rev 4; 8/11 Ultra-Low-Noise, High PSRR, Low-Dropout, 120mA Linear Regulators Features ♦ Space-Saving SC70 and TDFN 2mm x 2mm Packages ♦ 11µVRMS Output Noise at 100Hz to 100kHz Bandwidth (MAX8510) ♦ 78dB PSRR at 1kHz (MAX8510) ♦ 120mV Dropout at 120mA Load
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120mA
100Hz
100kHz
MAX8510)
120mV
MAX8511)
MAX8510/MAX8511)
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38K30
Abstract: DELTA39K CY3LV010
Text: USE DELTA39K FOR Quantum38K™ ISR™ ALL NEW DESIGNS CPLD Family CPLDs Designed for Migration Features • High density — 30K to 100K usable gates — 512 to 1536 macrocells — 136 to 302 maximum I/O pins — Eight dedicated inputs including four clock pins and
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DELTA39KTM
Quantum38KTM
16-Kb
48-Kb
125-MHz
18-mm
Quantum38K30
Quantum38K50
Quantum38K
Delta39K
38K30
CY3LV010
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100K preset horizontal
Abstract: LB 124 d LB 124 transistor verilog code for implementation of eeprom 38K30 j510
Text: Quantum38K ISR™ CPLD Family PRELIMINARY CPLDs Designed for Migration Features • High density — 30K to 100K usable gates — 512 to 1536 macrocells — 136 to 302 maximum I/O pins — Eight Dedicated Inputs including four clock pins and four global I/O control signal pins; four JTAG interface pins for reconfigurability/boundary scan
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Quantum38KTM
CY38K100
208-pin
208EQFP)
Quantum38K30
Quantum38K50
Quantum38K
100K preset horizontal
LB 124 d
LB 124 transistor
verilog code for implementation of eeprom
38K30
j510
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Untitled
Abstract: No abstract text available
Text: 19-4662; Rev 0; 6/09 Low-Noise, High PSRR, Low-Dropout, 120mA Linear Regulator Features ♦ Space-Saving SC70 ♦ 25µVRMS Output Noise at 100Hz to 100kHz Bandwidth ♦ 65dB PSRR at 10kHz ♦ 120mV Dropout at 120mA Load ♦ Stable with 1µF Ceramic Capacitor for Any Load
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120mA
100Hz
100kHz
10kHz
120mV
MAX8940EXKxy-T
MAX8940
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Untitled
Abstract: No abstract text available
Text: Quantum38K ISR™ CPLD Family CPLDs Designed for Migration Features • High density — 30K to 100K usable gates — 512 to 1536 macrocells — 136 to 302 maximum I/O pins — Eight dedicated inputs including four clock pins and four global I/O control signal pins; four JTAG
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Quantum38Kâ
125-MHz
18-mm
Quantum38K30
Quantum38K50
Quantum38K
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preset resistor 10k
Abstract: 4.7k Preset preset 10k preset resistor preset 10k ohm 2.2k Preset 10K preset PRESET 10K DATASHEET relay,10A data sheet of preset 10k
Text: KEPTROL Counter, Timer or Ratemeter Features • Counter, Timer or Ratemeter • Counts Up To 100 kHz PRESET COUNTERS • 8 Digit Display • Input Scaling • Batch Counter • DC Output to Power Peripherals Sensors • NEMA 4X / IP65 Sealed Front Panel Applications:
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RS232
RS422
preset resistor 10k
4.7k Preset
preset 10k
preset resistor
preset 10k ohm
2.2k Preset
10K preset
PRESET 10K DATASHEET
relay,10A
data sheet of preset 10k
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208EQFP
Abstract: No abstract text available
Text: Quantum38K ISR™ CPLD Family CPLDs Designed for Migration Features • High density — 30K to 100K usable gates — 512 to 1536 macrocells — 136 to 302 maximum I/O pins — Eight dedicated inputs including four clock pins and four global I/O control signal pins; four JTAG
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Quantum38KTM
125-MHz
18-mm
Quantum38K30
Quantum38K50
Quantum38K
208EQFP
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MAX8940
Abstract: No abstract text available
Text: 19-4662; Rev 0; 6/09 Low-Noise, High PSRR, Low-Dropout, 120mA Linear Regulator Features ♦ Space-Saving SC70 ♦ 25µVRMS Output Noise at 100Hz to 100kHz Bandwidth ♦ ♦ ♦ ♦ ♦ 65dB PSRR at 10kHz 120mV Dropout at 120mA Load Stable with 1µF Ceramic Capacitor for Any Load
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120mA
100Hz
100kHz
10kHz
120mV
MAX8940EXKxy-T
MAX8940
MAX8940
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mark X51
Abstract: aar transistor
Text: 19-2732; Rev 3; 5/06 Ultra-Low-Noise, High PSRR, Low-Dropout, 120mA Linear Regulators Features ♦ Space-Saving SC70 and TDFN 2mm x 2mm Packages ♦ 11µVRMS Output Noise at 100Hz to 100kHz Bandwidth (MAX8510) ♦ 78dB PSRR at 1kHz (MAX8510) ♦ 120mV Dropout at 120mA Load
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120mA
MAX8510/MAX8511/MAX8512
120mV
MAX8510
100kHz.
MAX8511
MAX8512
MAX8510/MAX8511
mark X51
aar transistor
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Untitled
Abstract: No abstract text available
Text: 19-2662; Rev 0; 10/02 High-Efficiency, Triple-Output, Keep-Alive Power Supply for Notebook Computers Features The MAX1534 is a high-efficiency, triple-output power supply for keep-alive always on voltage rails. The 500mA buck regulator with an internal current-limited
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MAX1534
500mA
200kHz
MAX1534
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MAX843
Abstract: No abstract text available
Text: 19-0388; Rev 0; 4/95 V M y J X IV M Low-Noise, Regulated, -2V GaAsFET Bias The MAX840 offers both a -2V preset output and a -0.5V to -9.4V a d ju stab le output. The M AX843/M AX844 use an external positive control voltage to set the negative output voltage. Input voltage range for all the devices is
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MAX840
AX843/M
AX844
MAX843/MAX844
5B7LL51
0011B75
MAX840/MAX843/MAX844
MAX843/MAX844
001127t
MAX843
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Untitled
Abstract: No abstract text available
Text: / T u TECHNOLOGY r m _LT1176/LT1176-5 Step-Down Switching Regulator FCRTURCS tion. The power switch, all oscillator and control circuitry, • 1,2A On-Board Switch ■ 100kHz Switching Frequency The topology is a classic positive “buck” configuration but
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LT1176/LT1176-5
100kHz
I8255-
20-Lead
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