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    AMD XC6SLX9-3TQG144C

    IC FPGA 102 I/O 144TQFP
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    DigiKey XC6SLX9-3TQG144C Tray 527 1
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    AMD XC6SLX4-2CSG225I

    IC FPGA 132 I/O 225CSBGA
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    DigiKey XC6SLX4-2CSG225I Tray 215 1
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    Avnet Americas XC6SLX4-2CSG225I Tray 12 Weeks 1
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    AMD XC6SLX75-2FGG676C

    IC FPGA 408 I/O 676FBGA
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    DigiKey XC6SLX75-2FGG676C Tray 209 1
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    AMD XC6SLX16-3CSG324C

    IC FPGA 232 I/O 324CSBGA
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    DigiKey XC6SLX16-3CSG324C Tray 166 1
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    AMD XC6SLX45-2CSG484C

    IC FPGA 320 I/O 484CSBGA
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    DigiKey XC6SLX45-2CSG484C Tray 133 1
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    Find more XC6S price and stock on Findchips.com

    XC6S Datasheets (499)

    Part ECAD Model Manufacturer Description Curated Datasheet Type PDF
    XC6SLX100-2CSG484C Xilinx Embedded - FPGAs (Field Programmable Gate Array), Integrated Circuits (ICs), IC FPGA 338 I/O 484CSPBGA Original PDF
    XC6SLX100-2CSG484I Xilinx Embedded - FPGAs (Field Programmable Gate Array), Integrated Circuits (ICs), IC FPGA 338 I/O 484CSPBGA Original PDF
    XC6SLX100-2FG484C Xilinx Embedded - FPGAs (Field Programmable Gate Array), Integrated Circuits (ICs), IC FPGA 326 I/O 484FBGA Original PDF
    XC6SLX100-2FG484I Xilinx Embedded - FPGAs (Field Programmable Gate Array), Integrated Circuits (ICs), IC FPGA 326 I/O 484FBGA Original PDF
    XC6SLX100-2FG676C Xilinx Embedded - FPGAs (Field Programmable Gate Array), Integrated Circuits (ICs), IC FPGA 480 I/O 676FCBGA Original PDF
    XC6SLX100-2FG676I Xilinx Embedded - FPGAs (Field Programmable Gate Array), Integrated Circuits (ICs), IC FPGA 480 I/O 676FCBGA Original PDF
    XC6SLX100-2FGG484C Xilinx Embedded - FPGAs (Field Programmable Gate Array), Integrated Circuits (ICs), IC FPGA 326 I/O 484FBGA Original PDF
    XC6SLX100-2FGG484I Xilinx Embedded - FPGAs (Field Programmable Gate Array), Integrated Circuits (ICs), IC FPGA 326 I/O 484FBGA Original PDF
    XC6SLX100-2FGG676C Xilinx Embedded - FPGAs (Field Programmable Gate Array), Integrated Circuits (ICs), IC FPGA 480 I/O 676FBGA Original PDF
    XC6SLX100-2FGG676I Xilinx Embedded - FPGAs (Field Programmable Gate Array), Integrated Circuits (ICs), IC FPGA 480 I/O 676FBGA Original PDF
    XC6SLX100-3CSG484C Xilinx Embedded - FPGAs (Field Programmable Gate Array), Integrated Circuits (ICs), IC FPGA 338 I/O 484CSPBGA Original PDF
    XC6SLX100-3CSG484I Xilinx Embedded - FPGAs (Field Programmable Gate Array), Integrated Circuits (ICs), IC FPGA 338 I/O 484CSPBGA Original PDF
    XC6SLX100-3FG484C Xilinx Embedded - FPGAs (Field Programmable Gate Array), Integrated Circuits (ICs), IC FPGA 326 I/O 484FBGA Original PDF
    XC6SLX100-3FG484I Xilinx Embedded - FPGAs (Field Programmable Gate Array), Integrated Circuits (ICs), IC FPGA 326 I/O 484FBGA Original PDF
    XC6SLX100-3FG676C Xilinx Embedded - FPGAs (Field Programmable Gate Array), Integrated Circuits (ICs), IC FPGA 480 I/O 676FCBGA Original PDF
    XC6SLX100-3FG676I Xilinx Embedded - FPGAs (Field Programmable Gate Array), Integrated Circuits (ICs), IC FPGA 480 I/O 676FCBGA Original PDF
    XC6SLX100-3FGG484C Xilinx Embedded - FPGAs (Field Programmable Gate Array), Integrated Circuits (ICs), IC FPGA 326 I/O 484FBGA Original PDF
    XC6SLX100-3FGG484I Xilinx Embedded - FPGAs (Field Programmable Gate Array), Integrated Circuits (ICs), IC FPGA 326 I/O 484FBGA Original PDF
    XC6SLX100-3FGG676C Xilinx Embedded - FPGAs (Field Programmable Gate Array), Integrated Circuits (ICs), IC FPGA 480 I/O 676FBGA Original PDF
    XC6SLX100-3FGG676I Xilinx Embedded - FPGAs (Field Programmable Gate Array), Integrated Circuits (ICs), IC FPGA 480 I/O 676FBGA Original PDF
    ...

    XC6S Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    Untitled

    Abstract: No abstract text available
    Text: VPX Boards VPX-SLX VPX module with User-Configurable Spartan-6 FPGA Front Panel Mezzanine Bus AXM I/O Module 64 I/O or 32 LVDS Dual-Port SRAM 1M x 32 XC6SLX150 Dual Port SRAM 1M x 32 97 I/O PCIe Bus 4 lanes Flash Memory 16MB XC5VLX30T VPX 3U card with PCIe interface ◆ Logic-optimized Spartan-6 FPGA ◆ Air and conduction-cooled models


    Original     		PDF XC6SLX150 XC5VLX30T 32-BIT 125MHZ 64-BIT LX30T

    XC6slx4

    Abstract: xc6slx75t ChipScope XCLX75T XC4VLX25 CoolRunner SPARTAN 3an Spartan 3AN Kit spartan XI Spartan-3an
    Text: CoolRunner XPLA3 CoolRunner-II™ CoolRunner-IIA™ XC9500™ Series Spartan-3 XC3S50 - XC3S1500 Spartan-3A All Spartan-3AN All Spartan-3A DSP XC3SD1800A Spartan-3E All Spartan-6 XC6SLX4 - XC6SLX75T XA Xilinx Automotive Spartan-3 All Spartan-3: All Spartan-3A: All


    Original     		PDF XC9500TM XC3S50 XC3S1500 XC3SD1800A XC6SLX75T XC5VFX30T 64-bit 32-bit XC4VLX15, XC4VLX25 XC6slx4 xc6slx75t ChipScope XCLX75T XC4VLX25 CoolRunner SPARTAN 3an Spartan 3AN Kit spartan XI Spartan-3an

    xc3s500e fg320

    Abstract: xc3s1800a fgg 484 XC3S50A/AN VQ100 XC3S250E vqg100 XC3S400 PQ208 SPARTAN-3 XC3S400 pq208 architecture xc3s1600e fg320 LVCMOS33 CPG196
    Text: XI LI NX S PARTAN -6 FAM I LY FPGAS Spartan-6 LX FPGAs Spartan-6 LXT FPGAs Optimized for Lowest-Cost Logic, DSP, and Memory 1.2 Volt, 1.0 Volt Part Number XC6SLX4 XC6SLX9 XC6SLX16 XC6SLX25 XC6SLX45 XC6SLX75 XC6SLX100 XC6SLX150 XC6SLX25T XC6SLX45T XC6SLX75T


    Original     		PDF XC6SLX16 XC6SLX25 XC6SLX45 XC6SLX75 XC6SLX100 XC6SLX150 XC6SLX25T XC6SLX45T XC6SLX75T XC6SLX100T xc3s500e fg320 xc3s1800a fgg 484 XC3S50A/AN VQ100 XC3S250E vqg100 XC3S400 PQ208 SPARTAN-3 XC3S400 pq208 architecture xc3s1600e fg320 LVCMOS33 CPG196

    XC6LX16-CS324

    Abstract: XC6SLX16 XC6LX16 carte spartan 6 xc6lx16-cs324 Xilinx Spartan6 Design Kit Spartan-6 Xilinx Ethernet development SPARTAN 6 ethernet spartan6 Spartan-6 FPGA
    Text: SPARTAN-6 FPGA SP601 EVALUATION KIT ENTRY-LEVEL, LOW-COST FPGA DESIGN PLATFORM SPARTAN-6 FPGA SP601 EVALUATION KIT Accelerated Development Accelerate your Designs – Right Out of the Box • Fewer resources under tighter deadlines, new standards, and shifting requirements


    Original     		PDF SP601 XC6LX16-CS324 XC6SLX16 XC6LX16 carte spartan 6 xc6lx16-cs324 Xilinx Spartan6 Design Kit Spartan-6 Xilinx Ethernet development SPARTAN 6 ethernet spartan6 Spartan-6 FPGA

    Untitled

    Abstract: No abstract text available
    Text: Spartan-6 FPGA Clocking Resources User Guide UG382 v1.8 June 20, 2013 Notice of Disclaimer The information disclosed to you hereunder (the “Materials”) is provided solely for the selection and use of Xilinx products. To the maximum extent permitted by applicable law: (1) Materials are made available "AS IS" and with all faults, Xilinx hereby DISCLAIMS ALL


    Original     		PDF UG382

    UG628

    Abstract: No abstract text available
    Text: Spartan-6 FPGA Configuration User Guide UG380 v2.5 January 23, 2013 Notice of Disclaimer The information disclosed to you hereunder (the “Materials”) is provided solely for the selection and use of Xilinx products. To the maximum extent permitted by applicable law: (1) Materials are made available "AS IS" and with all faults, Xilinx hereby DISCLAIMS ALL


    Original     		PDF UG380 UG628

    Untitled

    Abstract: No abstract text available
    Text: DIN Twin-contact Connectors XC5 A Wide Variety of DIN Connectors That Conform to UL/CSA Standards. • Fully preserve the characteristics of normal DIN connectors while increasing the number of terminals available. ■ A wide product range to fit almost any application.


    Original     		PDF E103202) XC5E-2021 XC5E-2023 XC5E-3221 XC5E-3223 XC5E-4421 XC5E-4423 XC5E-5021 XC5E-5023 XC5E-6421

    DSP48A1

    Abstract: DSP48A1 UG389 UG389 XC6SL DSP48A1 post adder XC6SLX150T verilog code for barrel shifter 8 bit carry select adder verilog code verilog code for 16 bit carry select adder systolic multiplier and adder vhdl code
    Text: Spartan-6 FPGA DSP48A1 Slice User Guide [optional] UG389 v1.1 August 13, 2009 [optional] Xilinx is disclosing this user guide, manual, release note, and/or specification (the "Documentation") to you solely for use in the development of designs to operate with Xilinx hardware devices. You may not reproduce, distribute, republish, download, display, post, or transmit the


    Original     		PDF DSP48A1 UG389 DSP48A1 UG389 UG389 XC6SL DSP48A1 post adder XC6SLX150T verilog code for barrel shifter 8 bit carry select adder verilog code verilog code for 16 bit carry select adder systolic multiplier and adder vhdl code

    MITYSOM-1810F

    Abstract: B09p SPARTAN 6 xc6slx45 pin configuration
    Text: Critical Link, LLC www.criticallink.com MitySOM MitySOM-1810F Processor Card 5-MAR-2014 FEATURES • TI AM1810 ARM9 Application Processor -        375 MHz ARM926EJ-S MPU • 16 KB L1 Program Cache • 16 KB L1 Data Cache  8 KB Internal RAM


    Original     		PDF MitySOM-1810F 5-MAR-2014 AM1810 ARM926EJ-S XC6SLX45 Sof75 6SLX16 256MB 128MB B09p SPARTAN 6 xc6slx45 pin configuration

    Untitled

    Abstract: No abstract text available
    Text: 89 Spartan-6 FPGA Data Sheet: DC and Switching Characteristics Product Specification DS162 v3.0 October 17, 2011 Spartan-6 FPGA Electrical Characteristics Spartan -6 LX and LXT FPGAs are available in various speed grades, with -3 having the highest performance. The DC and


    Original     		PDF DS162

    verilog code for dual port ram with axi interface

    Abstract: XC6SLX25T-2CSG324 UG473 verilog code for dual port ram with axi lite interface XC6VLX75T-2FF784 hamming code in vhdl axi wrapper blk_mem_gen verilog code for pseudo random sequence generator in state diagram of AMBA AXI protocol v 1.0
    Text: LogiCORE IP Block Memory Generator v7.1 DS512 April 24, 2012 Product Specification Introduction LogiCORE IP Facts The Xilinx LogiCORE IP Block Memory Generator BMG core is an advanced memory constructor that generates area and performance-optimized memories


    Original     		PDF DS512 verilog code for dual port ram with axi interface XC6SLX25T-2CSG324 UG473 verilog code for dual port ram with axi lite interface XC6VLX75T-2FF784 hamming code in vhdl axi wrapper blk_mem_gen verilog code for pseudo random sequence generator in state diagram of AMBA AXI protocol v 1.0

    xc6slx150t

    Abstract: STR Y 6763 64 point FFT radix-4 VHDL documentation 16 point FFT radix-4 VHDL documentation verilog code for radix-4 complex fast fourier transform radix-2 DIT FFT vhdl program fft matlab code using 8 point DIT butterfly str 1096 XC6VLX75T vhdl code for simple radix-2
    Text: LogiCORE IP Fast Fourier Transform v8.0 DS808 July 25, 2012 Product Specification Introduction LogiCORE IP Facts The Xilinx LogiCORE IP Fast Fourier Transform FFT implements the Cooley-Tukey FFT algorithm, a computationally efficient method for calculating the


    Original     		PDF DS808 xc6slx150t STR Y 6763 64 point FFT radix-4 VHDL documentation 16 point FFT radix-4 VHDL documentation verilog code for radix-4 complex fast fourier transform radix-2 DIT FFT vhdl program fft matlab code using 8 point DIT butterfly str 1096 XC6VLX75T vhdl code for simple radix-2

    XC7K410TFFG676-3

    Abstract: XILINX ipic axi Xilinx ISE Design Suite 14.2 axi interconnect xilinx xc6vlx130t1ff ZYNQ-7000
    Text: LogiCORE IP AXI Timebase Watchdog Timer axi_timebase_wdt (v1.01.a) DS763 July 25, 2012 Product Specification Introduction LogiCORE IP Facts The Advanced eXtensible Lite (AXI) Timebase Watchdog Timer is a 32-bit peripheral that provides a 32-bit free-running timebase and watchdog timer.


    Original     		PDF DS763 32-bit ZynqTM-7000 XC7K410TFFG676-3 XILINX ipic axi Xilinx ISE Design Suite 14.2 axi interconnect xilinx xc6vlx130t1ff ZYNQ-7000

    winbond* W25Q

    Abstract: UG380 SPARTAN 6 Configuration UG628 SPARTAN 6 spi numonyx spartan 6 LX150 Spartan6 XC6SLX9 winbond w25q W25Q spi flash programmer schematic
    Text: Spartan-6 FPGA Configuration User Guide [optional] UG380 v1.0 June 24, 2009 [optional] Xilinx is disclosing this user guide, manual, release note, and/or specification (the "Documentation") to you solely for use in the development of designs to operate with Xilinx hardware devices. You may not reproduce, distribute, republish, download, display, post, or transmit the


    Original     		PDF UG380 winbond* W25Q UG380 SPARTAN 6 Configuration UG628 SPARTAN 6 spi numonyx spartan 6 LX150 Spartan6 XC6SLX9 winbond w25q W25Q spi flash programmer schematic

    X485T

    Abstract: AMBA AXI4 verilog code axi wrapper
    Text: Xilinx Design Tools: Release Notes Guide Vivado Design Suite and ISE Design Suite UG631 v2012.2, v14.2 July 25, 2012 Notice of Disclaimer The information disclosed to you hereunder (the “Materials”) is provided solely for the selection and use of Xilinx products. To the maximum


    Original     		PDF UG631 v2012 X485T AMBA AXI4 verilog code axi wrapper

    jesd79f

    Abstract: UG388 MT41J256M8xx-187E 8 XC6SLX9 MT41J256M8xx-187E ddr3 ram slot pin detail MT41J64M16xx-187E micron DDR3 pcb layout MT41K128M8 Spartan-6 LX45
    Text: Spartan-6 FPGA Memory Controller User Guide UG388 v2.3 August 9, 2010 Xilinx is disclosing this user guide, manual, release note, and/or specification (the "Documentation") to you solely for use in the development of designs to operate with Xilinx hardware devices. You may not reproduce, distribute, republish, download, display, post, or transmit the


    Original     		PDF UG388 com/pdf/technotes/ddr2/TN4708 com/pdf/technotes/ddr2/TN4720 TMS320C6454/5 jesd79f UG388 MT41J256M8xx-187E 8 XC6SLX9 MT41J256M8xx-187E ddr3 ram slot pin detail MT41J64M16xx-187E micron DDR3 pcb layout MT41K128M8 Spartan-6 LX45

    UG381

    Abstract: hitachi sr 2010 receiver oserdes2 DDR spartan6 HDMI verilog code ISERDES2 JESD79-3 XC6SLX Spartan-6 LX45 XC6slx45 xc6slx75
    Text: Spartan-6 FPGA SelectIO Resources User Guide UG381 v1.4 December 16, 2010 Xilinx is disclosing this user guide, manual, release note, and/or specification (the "Documentation") to you solely for use in the development of designs to operate with Xilinx hardware devices. You may not reproduce, distribute, republish, download, display, post, or transmit the


    Original     		PDF UG381 UG381 hitachi sr 2010 receiver oserdes2 DDR spartan6 HDMI verilog code ISERDES2 JESD79-3 XC6SLX Spartan-6 LX45 XC6slx45 xc6slx75

    SiP12107

    Abstract: SiC403A SiP12108 SiP12109
    Text: VISHAY SILICONIX www.vishay.com Power ICs Application Note FPGA Power Supply Considerations by Owain Bryant ABSTRACT An FPGA is a device that offers many logic elements - up to 1 million gates in a single device at this writing - as well as other functionality such as transceivers, PLLs, and MAC units for complex processing. FPGAs are becoming very powerful, and the


    Original     		PDF SiC401A/B SiC402A/B SiC403A/B SiP12107 05-Mar-13 SiC403A SiP12108 SiP12109

    M88E1111

    Abstract: 32K10K-400E3 JS28F256P30 W25Q64VSFIG M88E1111 ETHERNET ICS874001 Chrontel CH7301C-TF 32K10K-400 XC6SLX45T-3FGG484 schematic diagram epson r230
    Text: SP605 Hardware User Guide [Guide Subtitle] [optional] UG526 v1.1 November 9, 2009 [optional] Xilinx is disclosing this user guide, manual, release note, and/or specification (the "Documentation") to you solely for use in the development of designs to operate with Xilinx hardware devices. You may not reproduce, distribute, republish, download, display, post, or transmit the


    Original     		PDF SP605 UG526 DS606, UG381, DS614, DS643, MT41J64M16LA-187E) W25Q64VSFIG) JS28F256P30) EG-2121CA-200 M88E1111 32K10K-400E3 JS28F256P30 W25Q64VSFIG M88E1111 ETHERNET ICS874001 Chrontel CH7301C-TF 32K10K-400 XC6SLX45T-3FGG484 schematic diagram epson r230

    XC6SLX9-TQG144-2C

    Abstract: XC6SLX45-CSG324 XC6SLX16-CSG225 XC6SLX16-FTG256 XC6SLX16-CSG324 XC6SLX4-TQG144-2C XC6SLX45-CSG484 XC6SLX9-CSG225 XC3S1400A-FG676-4C/I XC6SLX45-FGG484
    Text: 32-Bit Initiator/Target v3 & v4 for PCI DS206 December 2, 2009 Product Specification v3.167 & v4.11 Features • Fully compliant 32-bit, 66/33 MHz Initiator/Target core for PCI • Customizable, programmable, single-chip solution • Pre-defined implementation for predictable timing


    Original     		PDF 32-Bit DS206 32-bit, XC6SLX9-TQG144-2C XC6SLX45-CSG324 XC6SLX16-CSG225 XC6SLX16-FTG256 XC6SLX16-CSG324 XC6SLX4-TQG144-2C XC6SLX45-CSG484 XC6SLX9-CSG225 XC3S1400A-FG676-4C/I XC6SLX45-FGG484

    XC6SLX45-CSG324

    Abstract: XC6SLX16-CSG324 XC6SLX45-CSG484 XC3SD3400AFG676 XC6SLX9-FTG256 XC6SLX45t-fgg484 XC6SLX16-CSG324-2C XC6SLX16-FTG256 XC6SLX45-FGG484 xc3s1400afg676
    Text: 64-Bit Initiator/Target v3 & v4 for PCI DS205 December 2, 2009 Product Specification v3.167 & v4.10 Features Core Facts • Fully compliant 64-bit, 66/33 MHz LogiCORE IP Initiator/Target core for PCI Resource Utilization 1 v4 Core v3 Core • Customizable, programmable, single-chip solution


    Original     		PDF 64-Bit DS205 64-bit, XC6SLX45-CSG324 XC6SLX16-CSG324 XC6SLX45-CSG484 XC3SD3400AFG676 XC6SLX9-FTG256 XC6SLX45t-fgg484 XC6SLX16-CSG324-2C XC6SLX16-FTG256 XC6SLX45-FGG484 xc3s1400afg676

    axi ethernet lite software example

    Abstract: zynq axi ethernet software example microblaze ethernet V101A microblaze axi ethernet lite microblaze ethernet lite
    Text: LogiCORE IP Ethernet Lite MAC v1.01a DS787 October 19, 2011 Product Specification Introduction LogiCORE IP Facts Table The LogiCORE IP AMBA AXI Ethernet Lite MAC (Media Access Controller) is designed to incorporate the applicable features described in the IEEE Std. 802.3


    Original     		PDF DS787 axi ethernet lite software example zynq axi ethernet software example microblaze ethernet V101A microblaze axi ethernet lite microblaze ethernet lite

    XC4VLX15-FF668

    Abstract: axi4 XC4VLX15-FF668-10 FIFO Generator User Guide XQR XQ artix7 ucf file XC6SLX150T-FGG484-2 LocalLink axi wrapper XILINX/fifo generator xilinx spartan
    Text: LogiCORE IP FIFO Generator v8.3 DS317 October 19, 2011 Product Specification Introduction The Xilinx LogiCORE IP FIFO Generator is a fully verified first-in first-out FIFO memory queue for applications requiring in-order storage and retrieval. The core provides an optimized solution for all FIFO


    Original     		PDF DS317 XC4VLX15-FF668 axi4 XC4VLX15-FF668-10 FIFO Generator User Guide XQR XQ artix7 ucf file XC6SLX150T-FGG484-2 LocalLink axi wrapper XILINX/fifo generator xilinx spartan

    d5200c

    Abstract: RAMB16BWER vhdl code SECDED Xilinx ISE Design Suite 14.2 XC6SLX45T RAMB18E1
    Text: LogiCORE IP AXI Block RAM BRAM Controller (v1.03a) DS777 July 25, 2012 Product Specification Introduction LogiCORE IP Facts Table The LogiCORE IP AXI Block RAM (BRAM) Controller is a soft IP core for use with the Xilinx Vivado™ Design Suite, Embedded Development Kit


    Original     		PDF DS777 ZynqTM-7000 d5200c RAMB16BWER vhdl code SECDED Xilinx ISE Design Suite 14.2 XC6SLX45T RAMB18E1