DQ111
Abstract: DQ139 DQ131
Text: UGSN7004A8HHF-256 Data sheets can be downloaded at www.unigen.com 256MB 8M x 144 2PCS FPM MODE DRAM MODULE FPM Mode buffered DIMM With ECC based on 18 pcs 8M x 8 DRAM with LVTTL, 8K Refresh 256MB 200pin DIMM (2PCS 128MB (8M x 144) module kit) FEATURES Single 5.0V ± 10% power supply
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UGSN7004A8HHF-256
2000mil)
256MB
256MB
200pin
128MB
200-Pin
DIMM25
DQ120
DQ121
DQ111
DQ139
DQ131
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DQ111
Abstract: No abstract text available
Text: SM544083U74S6UU June 6, 2000 Revision History • June 9, 2000 Added Command Truth Table, Mode Register Table and notes. Modified waveforms Auto Refresh (CBR cycle and Power Down Mode and Clock Mask). • March 24, 1999 Datasheet released. Corporate Headquarters: P. O. Box 1757, Fremont, CA 94538, USA • Tel:(510) 623-1231 • Fax:(510) 623-1434 • E-mail: info@smartm.com
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SM544083U74S6UU
128MByte
4Mx16
DQ111
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Untitled
Abstract: No abstract text available
Text: SM544028002BXGU September 1996 Rev 0 SMART Modular Technologies SM544028002BXGU 32MByte 2M x 144 CMOS DRAM Module - Buffered General Description Features The SM544028002BXGU is a high performance, 32-megabyte dynamic RAM module organized as 2M words by 144 bits, in a 100-pin, dual readout, leadless,
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SM544028002BXGU
32MByte
32-megabyte
100-pin,
72-bit
70/80ns
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BA5 marking
Abstract: DQ112-127 BA7 marking HMD4M144D9WG DQ113 BA6 marking BA6137 DQ99
Text: HANBit HMD4M144D9WG 64Mbyte 4Mx144 200-pin ECC Mode 4K Ref. DIMM Design 5V Part No. HMD4M144D9WG GENERAL DESCRIPTION The HMD4M144D9WG is a 4Mbit x 144bit dynamic RAM high-density memory module. The module consists of eight CMOS 4Mx16bit DRAMs in 50-pin TSOP packages and one CMOS 4M x 16bit DRAM in 50pin TSOP package
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HMD4M144D9WG
64Mbyte
4Mx144)
200-pin
HMD4M144D9WG
144bit
4Mx16bit
50-pin
16bit
BA5 marking
DQ112-127
BA7 marking
DQ113
BA6 marking
BA6137
DQ99
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DQ124
Abstract: DQ77 DQ100 DQ99 DQ87 DQ88 DQ111 DQ106 DQ72 DQ79
Text: UG016E14488HSG Data sheets can be downloaded at www.unigen.com 256M Bytes 16M x 144 bits EDO MODE DRAM MODULE EDO Mode buffered DIMM With ECC based on 36 pcs 8M x 8 DRAM with LVTTL, 8K Refresh PIN ASSIGNMENT (Front View) 200-Pin DIMM FEATURES 256MB (16 Meg x 144)
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UG016E14488HSG
200-Pin
256MB
2560mil)
DQ124
DQ77
DQ100
DQ99
DQ87
DQ88
DQ111
DQ106
DQ72
DQ79
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DQ112
Abstract: UG016C14488HSG-6 DQ100 DQ88
Text: UG016C14488HSG Data sheets can be downloaded at www.unigen.com 256M Bytes 16M x 144 bits FPM MODE DRAM MODULE FPM Mode buffered DIMM With ECC based on 36 pcs 8M x 8 DRAM with LVTTL, 8K Refresh PIN ASSIGNMENT (Front View) 200-Pin DIMM FEATURES 256MB (16 Meg x 144)
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UG016C14488HSG
200-Pin
256MB
2560mil)
DQ112
UG016C14488HSG-6
DQ100
DQ88
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J32CG
Abstract: 61a3 mosfet BCM5461KFB 61a3 58A6 bcm5461 60F10 L32SD DQ27152 A26B4
Text: 1 2 4 3 5 6 7 TABLE OF CONTENTS F F PAGE 02 - BLOCK DIAGRAM PAGE 03 - 750GX ADDRESS/DATA BUSSES PAGE 04 - 750GX CONTROLS AND GROUND PAGE 05 - 750GX POWER AND DECOUPLING PAGE 06 - TSI108 PROCESSOR BUS INTERFACE PAGE 07 - TSI108 MEMORY INTERFACE PAGE 08 - DDR2 DIMM CONNECTOR SLOT 0
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750GX
TSI108
RS232
NC7SZ00
J32CG
61a3 mosfet
BCM5461KFB
61a3
58A6
bcm5461
60F10
L32SD
DQ27152
A26B4
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Untitled
Abstract: No abstract text available
Text: UG08E14488HSG-6 128M Bytes 8M x 144 DRAM 200Pin DIMM w/ECC based on 8M x 8 General Description Features The U08E14488HSG-6 is a 8M x 144 200pin DIMM. The module is organized as a 8M x 144 high speed memory array and optimized for use in ECC applications. This module consist of 18 pcs 8M x 8
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UG08E14488HSG-6
200Pin
U08E14488HSG-6
400mil
16bit
240mil
2000mil)
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DQ2060
Abstract: DC1065 EB285 EBSA-285 R164 SA110 B20B20 A59A59 CPU-A13 CPUD22
Text: A B C D COPYRIGHT C 8 1997 DIGITAL EQUIPMENT CORPORATION 8 16 17 18 19 20 21 sht sht sht sht sht sht 7 CHK CHANGE NO. REV CPU, CPU_, a Block Address X-Bus XBUF_, have PCI +3V Stand - +2V, - - - TAG_,RST_ - - 6 bidirects this 5 is Debug Port their Serial Spare
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ebsa285
220PF
RS232
DQ2060
DC1065
EB285
EBSA-285
R164
SA110
B20B20
A59A59
CPU-A13
CPUD22
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Untitled
Abstract: No abstract text available
Text: UG016C14488HSG-6 256M Bytes 16M x 144 DRAM 200Pin DIMM w/ECC based on 8M x 8 General Description Features The U016C14488HSG-6 is a 16M x 144 200pin DIMM. The module is organized as a 16M x 144 high speed memory array and optimized for use in ECC applications. This module consist of 36 pcs 8M x 8
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UG016C14488HSG-6
200Pin
U016C14488HSG-6
400mil
20bit
240mil
2560mil)
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MT18DT8144G
Abstract: No abstract text available
Text: 8 MEG x 144 BUFFERED DRAM DIMM DRAM MODULE MT18DT8144G For the latest data sheet, please refer to the Micron Web site: www.micron.com/mti/msp/html/datasheet.html FEATURES PIN ASSIGNMENT • • • • • • • 200-pin, dual in-line memory module DIMM
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200-pin,
128MB
192-cycle
MT18DT8144G
DQ995
MT18DT8144G
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sanyo LCD camera display
Abstract: LC5860 sanyo lcd clock display
Text: SANYO SEMI CONDUCTOR CORP b3E D • 7Tì707b DQ111G1 bb3 I TSAJ CMOS 4-BIT SINGLE-CHIP MICROCOMPUTERS LC5860/5870 SERIES Overview The LC5860/5870 Series CMOS 4-bit single-chip micro computers are ideal for controlling LCD displays. Sanyo's proprietary LCD display circuit technology controller/
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DQ111G1
LC5860/5870
256-/512-word
15-bit
sanyo LCD camera display
LC5860
sanyo lcd clock display
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Untitled
Abstract: No abstract text available
Text: -P R E L IM IN A R Y October 1995 Edition 1.1 = FUJITSU PRODUCT PROFILE SHEET MB 8 116165 A- 60/-70 CMOS 1M X 16BIT HYPER PAGE M O D E DYNAMIC RAM CMOS 1,048,576 x 16BIT Hyper Page Mode Dynamic RAM The Fujitsu MB8116165A is a fully decoded CMOS Dynamic RAM DRAM that contains
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16BIT
MB8116165A
16-bit
256-bits
MB8116165A-60
MB8116165A-70
50-LEAD
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Untitled
Abstract: No abstract text available
Text: IBM14N1372 IBM14N3272 IBM14N6472 High Perform ance SRAM Modules Features • 256K, 512K, and 1MB secondary cache module family using Synchronous and Asynchronous SRAMs. • Organized as a 32K, 64K, or 128K x 72 package on a 4.3” x 1.1”, 160-lead, Dual Read-out DIMM
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IBM14N1372
IBM14N3272
IBM14N6472
160-lead,
i486/PentiumTM
50MHz
66MHz
256KB,
512KB,
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Untitled
Abstract: No abstract text available
Text: FDC37C93XFR SMC ADVANCE INFORMATION STANDARD M IC R O SY ST EM S CORPORATION Plug and Play Compatible Ultra I/O Controller with Fast IR FEATURES ISA Plug-and-Play Standard {Version 1.Oa Compatible Register Set Soft Power Management, SMI Support ACCESS.bus Support
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FDC37C93XFR
MC146818
DS1287
65BSC
00120S4
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TME 57
Abstract: DQ131 45VCci a81s DQ111 A5173
Text: m EDI9F232256BC 1 2x256Kx32 SRAM Module x ELECTRONIC DESIGNI N C. 2x256Kx32 Static RAM CMOS, High SpeedModule Features The EDI9F232256B is a high speed 16 megabit Static RAM module organized as 2x256K words by 32 bits. This module is constructed from sixteen 256Kx4 Static RAMs in SOJ
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EDI9F232256BC
2x256Kx32
EDI9F232256B
2x256K
256Kx4
2322568RW
TME 57
DQ131
45VCci
a81s
DQ111
A5173
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Untitled
Abstract: No abstract text available
Text: MITSUBISHI LSIs M5M564R16CJ.TP-10,-12,-15 í f at Nc*,ce » • uSume Pdid 1048576-BIT 65536-WORD BY 16-BIT CMOS STATIC RAM DESCRIPTION The M5M564R16C is a family of 65536-word by 16-bit static RAMs, fabricated with the high performance CMOS process and
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M5M564R16CJ
TP-10
1048576-BIT
65536-WORD
16-BIT)
M5M564R16C
16-bit
AO-15
DQt-16
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TI AIH
Abstract: R 161 730 000
Text: O K I Semiconductor MSM51 V17160 1,048,576-Word x 16-Bit DYNAMIC RAM : FAST PAGE MODE TYPE DESCRIPTION The MSM51V17160 is a new generation Dynamic RAM organized as 1,048,576-word x 16-bit configuration. The technology used to fabricate the MSM51V17160 is OKI's CMOS silicon gate process technology.
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MSM51VI7160
576-Word
16-Bit
MSM51V17160
cycles/32ms
TI AIH
R 161 730 000
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4744AP
Abstract: 4744a 32P4741
Text: SSI 32P4741 /4744/4744A Read Channel with 1,7 ENDEC, 4-burst Servo s lim s q s b n s A TDK Group/Company January 1995 DESCRIPTION FEATURES The SSI 32P4741/4744/4744A devices are high performance BiCMOS single chip read channel ICs that contain all the functions needed to implement a
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32P4741
/4744/4744A
32P4741/4744/4744A
32P4741/4744/
32P4741-CGT
32P4744-CGT
32P4744A-CGT
32P4744A-CGT
4744AP
4744a
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Untitled
Abstract: No abstract text available
Text: HITACHI/ LI NEA R D E V I C E S 2bE ]> 4Mcib2Q 2 Q 01113R 1 H A 1 2 1 3 2 M P - p n - z i A/D, D/A Converter with Built-in S/H Circuit Pin Arrangement Description T h e H itach i H A 12132 is a 16 b it A /D , D /A converter operating on a single 5 V supply. It is
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01113R
HA12132MP
HA12132
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MT4C1670
Abstract: No abstract text available
Text: MICRON TECHNOLOGY INC 5SE T> • falllSHI DD0HS21 SbT ■ URN MT4C1670/1 L 64K X 16 DRAM MICRON rn TECHNOLOGY INC. DRAM 6 4 K x 1 6 DRAM NEW T -w -zb -n STATIC COLUMN MODE, LOW POWER, EXTENDED REFRESH • Industry standard xl6 pinouts, timing, functions and packages
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DD0HS21
MT4C1670/1
MT4C1670
MT4C1671
225mW-----------
DDD4S36
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MAGNETIC HEAD tape deck
Abstract: BA3402 audio MAGNETIC HEAD car wiring diagram MAGNETIC HEAD audio Y58M ZIP16 MAGNETIC HEAD 8 channel equalizer MAGNETIC HEAD impedance
Text: Audio ICs Dual-channel, auto-reverse tape preamplifier BA3402 T h e B A 3 4 0 2 is a d u a l p r e a m p lifie r d e v e lo p e d fo r a u to -r e v e r s e c a r ta p e d e c k s . A n e le c tr o n ic s w itc h on th e c h ip s w itc h e s b e tw e e n th e fo rw a rd a n d re v e rs e h e a d s , a n d this h a s th e b e n efits o f g re a te r reliab ility, e a s ie r w iring , lo w er
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BA3402
BA3402
6XR3X10Qvc
3180X10-6
ZIP16
MAGNETIC HEAD tape deck
audio MAGNETIC HEAD
car wiring diagram
MAGNETIC HEAD audio
Y58M
ZIP16
MAGNETIC HEAD
8 channel equalizer
MAGNETIC HEAD impedance
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Untitled
Abstract: No abstract text available
Text: D S 1 2 3 0 Y /A B DALLAS SEMICONDUCTOR FEATURES DS1 230Y/ AB 256K N onvolatile SRAM PIN ASSIGNMENT A14 111 281 A12 112 E 271IW A7 113 261IA13 A6 114 251IA8 A5 115 241IA9 A4 116 231IA11 A3 117 221I A2 118 211I A10 A1 119 201I^ A0 1110 191I DQ7 DQ01111 181I DQe
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DS1230Y)
DS1230AB)
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Untitled
Abstract: No abstract text available
Text: 31E D GEC PLESSEY SEMICONDS 37basaaoouw ^FLESSEY W i • H T '5 0 - 0 ° \ S em icon d u cto rs. NJ8820, NJ8820B FREQUENCY SYNTHESISER PROM INTERFACE The NJ8820/NJ8820B is a synthesiser circuit fabricated on the Plessey 5-micron CMOS process and is capable of
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37basaaoouw
NJ8820,
NJ8820B
NJ8820/NJ8820B
11bit
10-bit
520MHz
NJ8820/NJ8820B
T-50-09
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