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    SINGLE EVENT UPSET FPGA Search Results

    SINGLE EVENT UPSET FPGA Result Highlights (5)

    Part ECAD Model Manufacturer Description Download Buy
    FO-9LPBMTRJ00-001 Amphenol Cables on Demand Amphenol FO-9LPBMTRJ00-001 MT-RJ Connector Loopback Cable: Single-Mode 9/125 Fiber Optic Port Testing .1m Datasheet
    AV-THLIN2RCAM-005 Amphenol Cables on Demand Amphenol AV-THLIN2RCAM-005 Thin-line Single RCA Coaxial Cable - RCA Male / RCA Male (Coaxial Digital Audio Compatible) 5ft Datasheet
    CS-SASSDP8282-001 Amphenol Cables on Demand Amphenol CS-SASSDP8282-001 29 position SAS to SATA Drive Connector Single Data Lane Cable 1m Datasheet
    FO-DLSCDLLC00-002 Amphenol Cables on Demand Amphenol FO-DLSCDLLC00-002 SC-LC Duplex Single-Mode 9/125 Fiber Optic Patch Cable (OFNR Riser) - 2 x SC Male to 2 x LC Male 2m Datasheet
    FO-LSDUALSCSM-003 Amphenol Cables on Demand Amphenol FO-LSDUALSCSM-003 SC-SC Duplex Single-Mode 9/125 Fiber Optic Patch Cable (OFN-LS Low Smoke) - 2 x SC Male to 2 x SC Male 3m Datasheet

    SINGLE EVENT UPSET FPGA Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    voting elements

    Abstract: 40MX 42MX 54SX AC134 voting
    Text: Application Note AC134 Minimizing Single Event Upset Effects Using Synopsys This application note gives an overview of some single event upset SEU resistant design techniques and describes how to implement these techniques using Synopsys. Familiarity with the Synopsys FPGA Compiler tool and “dc_shell” script


    Original     		PDF AC134 voting elements 40MX 42MX 54SX AC134 voting

    BR2477a

    Abstract: BR1220 FIPS-197 implement 16-bit CRC in transmitter and receiver
    Text: Section IV. Design Security and Single Event Upset SEU Mitigation This section provides information on Design Security and Single Event Upset (SEU) Mitigation in Stratix III devices. Revision History Altera Corporation • Chapter 14, Design Security in Stratix III Devices


    Original     		PDF SIII51 BR2477a BR1220 FIPS-197 implement 16-bit CRC in transmitter and receiver

    Untitled

    Abstract: No abstract text available
    Text: Appl i cat i o n N ot e Minimizing Single Event Upset Effects Using Synopsys This application note gives an overview of some single event upset SEU resistant design techniques and describes how to implement these techniques using Synopsys. Familiarity with the Synopsys FPGA Compiler tool and “dc_shell” script


    Original     		PDF

    BR1220

    Abstract: BR2477A FIPS-197
    Text: Section IV. Design Security and Single Event Upset SEU Mitigation This section provides information on Design Security and Single Event Upset (SEU) Mitigation in Stratix III devices. • Chapter 14, Design Security in Stratix III Devices ■ Chapter 15, SEU Mitigation in Stratix III Devices


    Original     		PDF 20dated BR1220 BR2477A FIPS-197

    Synplify tmr

    Abstract: aadl sequential logic
    Text: v3.0 9-2-98 Appl i cat i o n N ot e Minimizing Single Event Upset Effects Using Synplicity This application note gives an overview of some single event upset SEU resistant design techniques and describes how to implement these techniques using Synplicity Synplify 3.0C


    Original     		PDF

    XAPP987

    Abstract: voter XAPP988 XAPP216 RAM SEU fpga radiation CREME96 Upsets XAPP779 XQR2V6000
    Text: Application Note: FPGAs Single-Event Upset Mitigation Selection Guide R Author: Brendan Bridgford, Carl Carmichael, and Chen Wei Tseng XAPP987 v1.0 March 18, 2008 Summary This application note discusses different aspects of single-event upsets and recommends


    Original     		PDF XAPP987 XAPP987 voter XAPP988 XAPP216 RAM SEU fpga radiation CREME96 Upsets XAPP779 XQR2V6000

    UG156

    Abstract: single port ram testbench vhdl SRL16 XAPP962 XAPP987 Virtex-4 radiation XAPP1004 XAPP216 XC2VP40 XC4VLX200
    Text: Application Note: Virtex-II, and Virtex-4 FPGAs R XAPP962 v1.1 March 14, 2008 Summary Single-Event Upset Mitigation for Xilinx FPGA Block Memories Authors: Greg Miller, Carl Carmichael, and Gary Swift Orbital, space-based, and extra-terrestrial applications are susceptible to the effects of highenergy charged particles. If of sufficient energy, these particles can cause single-event upsets


    Original     		PDF XAPP962 UG156 single port ram testbench vhdl SRL16 XAPP962 XAPP987 Virtex-4 radiation XAPP1004 XAPP216 XC2VP40 XC4VLX200

    RAM EDAC SEU

    Abstract: SRAM edac AC304 sram 2114 edac 2114 SRAM RAM SEU RAM64k36 7 bit hamming code hamming code
    Text: Application Note AC304 Simulating SEU Events in EDAC RAM Introduction The Actel RTAX-S Field Programmable Gate Array FPGA provides embedded user static RAM in addition to single-event-upset (SEU)-enhanced logic, including embedded triple-module redundancy (TMR)


    Original     		PDF AC304 RAM EDAC SEU SRAM edac AC304 sram 2114 edac 2114 SRAM RAM SEU RAM64k36 7 bit hamming code hamming code

    Actel a1280

    Abstract: A1280 ACTEL burn-in VKS FPGA CQFP 106 A1020 RH1020 RH1280 RT1020 lockheed-martin CQFP 172 PIN
    Text: v3.1 Radiation-Hardened FPGAs Features • • • • • • • • Guaranteed Total Dose Radiation Capability Low Single Event Upset Susceptibility High Dose Rate Survivability Latch-Up Immunity Guaranteed QML Qualified Devices Commercial Devices Available for Prototyping and


    Original     		PDF

    actel die run marking

    Abstract: No abstract text available
    Text: v3.1 Radiation-Hardened FPGAs Features • • • • • • • • Guaranteed Total Dose Radiation Capability Low Single Event Upset Susceptibility High Dose Rate Survivability Latch-Up Immunity Guaranteed QML Qualified Devices Commercial Devices Available for Prototyping and


    Original     		PDF

    CQFP 172 PIN

    Abstract: A1280 Actel a1280 RH1280 RH1020 VKS FPGA CQFP 172 transistor a1020 VKS FPGA CQFP 106 A1020 RT1020
    Text: v3.1 Radiation-Hardened FPGAs Features • • • • • • • • Guaranteed Total Dose Radiation Capability Low Single Event Upset Susceptibility High Dose Rate Survivability Latch-Up Immunity Guaranteed QML Qualified Devices Commercial Devices Available for Prototyping and


    Original     		PDF

    actel cqfp 84

    Abstract: No abstract text available
    Text: v3.1 Radiation-Hardened FPGAs Features • • • • • • • • Guaranteed Total Dose Radiation Capability Low Single Event Upset Susceptibility High Dose Rate Survivability Latch-Up Immunity Guaranteed QML Qualified Devices Commercial Devices Available for Prototyping and


    Original     		PDF

    Actel a1280

    Abstract: RH1020 RH1020 datasheet RH1280 transistor a1020 VKS FPGA CQFP 106 A1020 A1280 marking 8AG lockheed-martin
    Text: v3.0 Radiation-Hardened FPGAs Fe a t ur es • Non-Volatile, User Programmable Devices • Guaranteed Total Dose Radiation Capability • Fabricated in 0.8µ Epitaxial Bulk CMOS Process • Low Single Event Upset Susceptibility • High Dose Rate Survivability


    Original     		PDF A1280 A1020 Actel a1280 RH1020 RH1020 datasheet RH1280 transistor a1020 VKS FPGA CQFP 106 marking 8AG lockheed-martin

    RH1020

    Abstract: A1020 A1280 CQ84 RH1280
    Text: Radiation-Hardened Field Programmable Gate Arrays Features • Guaranteed Total Dose Radiation Capability • Low Single Event Upset Susceptibility • High Dose Rate Survivability • Latch-Up Immunity Guaranteed • QML Qualified Devices • Commercial Devices Available for Prototyping and


    Original     		PDF RH1020 RH1280 RH1020 A1020 A1280 CQ84 RH1280

    RTSX32SU CQ84 PROTO

    Abstract: RTSX32SU CQ84 RTSX72SU1 SOC 8A fuse smd RTSX32su CG624 thermal expansion
    Text: Revision 9 RTSX-SU Radiation-Tolerant FPGAs UMC Designed for Space • SEU-Hardened Registers Eliminate the Need to Implement Triple-Module Redundancy (TMR) – Immune to Single Event Upsets (SEU) to LETth > 40 MeVcm2/mg, – SEU Rate < 10–10 Upset/Bit-Day in Worst-Case


    Original     		PDF TM1019 RTSX32SU CQ84 PROTO RTSX32SU CQ84 RTSX72SU1 SOC 8A fuse smd RTSX32su CG624 thermal expansion

    0116 solar 4 pins

    Abstract: 8ag marking equivalent transistor A1020 y 7 b RH1280
    Text: v 2. 0 Radiation-Hardened Field Programmable Gate Arrays Features • Guaranteed Total Dose Radiation Capability • Low Single Event Upset Susceptibility • High Dose Rate Survivability • Latch-Up Immunity Guaranteed • QML Qualified Devices • Commercial Devices Available for Prototyping and


    Original     		PDF 20-Pin RH1020 RH1280 CQ208 CQ256, 0116 solar 4 pins 8ag marking equivalent transistor A1020 y 7 b

    32 BIT ALU design with vhdl Xilinx ISE 8.2i

    Abstract: xc4fx20-10ff672 ML405 ucf file 83-ISP UG156 32 BIT ALU design with vhdl RAMB16 XAPP1004 XC4VFX20 ML405
    Text: Application Note: Virtex-4 FX FPGAs Single-Event Upset Mitigation Design Flow for Xilinx FPGA PowerPC Systems R XAPP1004 v1.0 March 14, 2008 Summary Authors: Greg Miller, Carl Carmichael, and Gary Swift Orbital, space-based, and extra-terrestrial applications are susceptible to the effects of high


    Original     		PDF XAPP1004 32 BIT ALU design with vhdl Xilinx ISE 8.2i xc4fx20-10ff672 ML405 ucf file 83-ISP UG156 32 BIT ALU design with vhdl RAMB16 XAPP1004 XC4VFX20 ML405

    Synplify tmr

    Abstract: voter vhdl code for a grey-code counter CC16CE MUXCY CC16SE SRL16 XAPP197 XAPP216 vhdl coding for hamming code
    Text: Application Note: Virtex Series R XAPP197 v1.0.1 July 6, 2006 Triple Module Redundancy Design Techniques for Virtex FPGAs Author: Carl Carmichael Summary Triple Module Redundancy (TMR) combined with Single Event Upset (SEU) correction through partial reconfiguration is a powerful and effective SEU mitigation strategy. This method is only


    Original     		PDF XAPP197 XAPP216, XAPP216 Synplify tmr voter vhdl code for a grey-code counter CC16CE MUXCY CC16SE SRL16 XAPP197 vhdl coding for hamming code

    Untitled

    Abstract: No abstract text available
    Text: 9 SEU Mitigation for Stratix V Devices 2013.05.06 SV51011 Subscribe Feedback This chapter describes the error detection features in Stratix V devices. You can use these features to mitigate single event upset SEU or soft errors. Related Information Stratix V Device Handbook: Known Issues


    Original     		PDF SV51011

    Synplify tmr

    Abstract: CC16CE vhdl code hamming edac memory vhdl code for a grey-code counter XAPP216 voter CC16RE vhdl coding for error correction and detection algorithms vhdl code hamming RAM EDAC SEU
    Text: Application Note: Virtex Series R XAPP197 v1.0 November 1, 2001 Triple Module Redundancy Design Techniques for Virtex FPGAs Author: Carl Carmichael Summary Triple Module Redundancy (TMR) combined with Single Event Upset (SEU) correction through partial reconfiguration is a powerful and effective SEU mitigation strategy. This method is only


    Original     		PDF XAPP197 XAPP216, XAPP216 Synplify tmr CC16CE vhdl code hamming edac memory vhdl code for a grey-code counter voter CC16RE vhdl coding for error correction and detection algorithms vhdl code hamming RAM EDAC SEU

    ACTEL CCGA 624 mechanical

    Abstract: 208-Pin CQFP Actel a54sx72a tid CCGA -CG 472
    Text: v2 . 2 RTSX-S RadTolerant FPGAs Designed for Space • • • • • SEU-Hardened Registers Eliminate the Need to Implement Triple-Module Redundancy TMR – Immune to Single-Event Upsets (SEU) to LETth > 40 MeV-cm2/mg, – SEU Rate < 10–10 Upset/Bit-Day in Worst-Case


    Original     		PDF TM1019 ACTEL CCGA 624 mechanical 208-Pin CQFP Actel a54sx72a tid CCGA -CG 472

    Untitled

    Abstract: No abstract text available
    Text: Æ ic te - m ! v 2 .0 Radiation-Hardened Field Programmable Gate Arrays Features Guaranteed Total Dose Radiation Capability Low Single Event Upset Susceptibility High Dose Rate Survivability Latch-Up Im m unity Guaranteed QML Qualified Devices


    OCR Scan     		PDF RH1020 RH1280 CCS08and CQ256,

    h128 transistor

    Abstract: transistors H128 NH FUSE LINDER BSC 25-05 quivalent book
    Text: RadHard Field Programmable Gate Arrays F e a ftw s re s Guaranteed Total Dose Radiation Capability Low Single Event Upset Susceptibility High D oseR ateS urvivability Latch-Up Im m unity Guaranteed QML Qualified Devices Commercial Devices A vailablefor Prototyping and


    OCR Scan     		PDF 20-Pin h128 transistor transistors H128 NH FUSE LINDER BSC 25-05 quivalent book

    2001TL

    Abstract: actel die run marking
    Text: Æ lctel Radiation-Hardened Field Programmable Gate Arrays F e a tu re s • Guaranteed Total Dose Radiation Capability • Low Single Event Upset Susceptibility • High Dose Rate Survivability • Latch-Up Immunity Guaranteed • QML Qualified Devices • Commercial Devices Available for Prototyping and


    OCR Scan     		PDF 20-Pin RH1020 RH1280 RH1280 2001TL actel die run marking